Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 467
PIC18F87J50 FAMILY
PIC18F87J50 Family Devices ........................... 79
Shared Address Registers ................................. 82
Special Function Registers ................................ 81
Special Function Registers ........................................ 81
Context Defined SFRs ....................................... 82
USB RAM ................................................................... 78
DAW ................................................................................. 384
DC Characteristics ........................................................... 430
Power-Down and Supply Current ............................ 422
Supply Voltage ......................................................... 421
DCFSNZ .......................................................................... 385
DECF ............................................................................... 384
DECFSZ ........................................................................... 385
Development Support ...................................................... 415
Device Differences ........................................................... 463
Device Overview .................................................................. 9
Details on Individual Family Members ....................... 10
Features (64-Pin Devices) ......................................... 11
Features (80-Pin Devices) ......................................... 11
Direct Addressing ............................................................... 91
E
ECCP
Associated Registers ............................................... 232
Capture and Compare Modes .................................. 220
Enhanced PWM Mode ............................................. 221
Standard PWM Mode ............................................... 220
Effect on Standard PIC Instructions ................................. 412
Electrical Characteristics .................................................. 419
Enhanced Capture/Compare/PWM (ECCP) .................... 217
Capture Mode. See Capture (ECCP Module).
ECCP1/ECCP3 Outputs and Program Memory Mode ...
218
ECCP2 Outputs and Program Memory Modes ........ 218
Outputs and Configuration ....................................... 218
Pin Configurations for ECCP1 ................................. 219
Pin Configurations for ECCP2 ................................. 219
Pin Configurations for ECCP3 ................................. 220
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 218
Use of CCP4/CCP5 with ECCP1/ECCP3 ................ 218
Enhanced Universal Synchronous Asynchronous Receiver
Transmitter (EUSART). See EUSART.
ENVREG pin .................................................................... 360
Equations
A/D Acquisition Time ................................................ 306
A/D Minimum Charging Time ................................... 306
Calculating the Minimum Required Acquisition Time .....
306
Estimating USB Transceiver Current Consumption . 333
Errata ................................................................................... 7
EUSART
Asynchronous Mode ................................................ 289
12-Bit Break Transmit and Receive ................. 294
Associated Registers, Receive ........................ 292
Associated Registers, Transmit ....................... 290
Auto-Wake-up on Sync Break ......................... 292
Receiver ........................................................... 291
Setting Up 9-Bit Mode with Address Detect ..... 291
Transmitter ....................................................... 289
Baud Rate Generator
Operation in Power-Managed Mode ................ 283
Baud Rate Generator (BRG) .................................... 283
Associated Registers ....................................... 284
Auto-Baud Rate Detect .................................... 287
Baud Rate Error, Calculating ........................... 284
Baud Rates, Asynchronous Modes ................. 285
High Baud Rate Select (BRGH Bit) ................. 283
Sampling ......................................................... 283
Synchronous Master Mode ...................................... 295
Associated Registers, Receive ........................ 298
Associated Registers, Transmit ....................... 296
Reception ........................................................ 297
Transmission ................................................... 295
Synchronous Slave Mode ........................................ 298
Associated Registers, Receive ........................ 300
Associated Registers, Transmit ....................... 299
Reception ........................................................ 299
Transmission ................................................... 298
Extended Instruction Set
ADDFSR .................................................................. 408
ADDULNK ............................................................... 408
CALLW .................................................................... 409
MOVSF .................................................................... 409
MOVSS .................................................................... 410
PUSHL ..................................................................... 410
SUBFSR .................................................................. 411
SUBULNK ................................................................ 411
External Clock Input ........................................................... 38
External Memory Bus ...................................................... 107
16-Bit Byte Select Mode .......................................... 113
16-Bit Byte Write Mode ............................................ 111
16-Bit Data Width Modes ......................................... 110
16-Bit Mode Timing ................................................. 114
16-Bit Word Write Mode .......................................... 112
8-Bit Data Width Mode ............................................ 115
8-Bit Mode Timing ................................................... 116
Address and Data Line Usage (table) ..................... 109
Address and Data Width .......................................... 109
Address Shifting ...................................................... 109
Control ..................................................................... 108
I/O Port Functions .................................................... 107
Operation in Power-Managed Modes ...................... 117
Program Memory Modes ......................................... 110
Extended Microcontroller ................................. 110
Microcontroller ................................................. 110
Wait States .............................................................. 110
Weak Pull-ups on Port Pins ..................................... 110
F
Fail-Safe Clock Monitor ........................................... 349, 362
Interrupts in Power-Managed Modes ...................... 363
POR or Wake-up From Sleep .................................. 363
WDT During Oscillator Failure ................................. 362
Fast Register Stack ........................................................... 75
Firmware Instructions ...................................................... 365
Flash Configuration Words .............................................. 349
Flash Program Memory ..................................................... 97
Associated Registers ............................................... 106
Control Registers ....................................................... 98
EECON1 and EECON2 ..................................... 98
TABLAT (Table Latch) Register ...................... 100
TBLPTR (Table Pointer) Register .................... 100
Erase Sequence ...................................................... 102
Erasing .................................................................... 102
Operation During Code-Protect ............................... 106
Reading ................................................................... 101
Table Pointer
Boundaries Based on Operation ..................... 100
Table Pointer Boundaries ........................................ 100
Table Reads and Table Writes .................................. 97
Write Sequence ....................................................... 103