Datasheet

PIC18F87J50 FAMILY
DS39775C-page 466 © 2009 Microchip Technology Inc.
Detecting .................................................................... 57
Disabling in Sleep Mode ............................................ 57
BSF .................................................................................. 377
BTFSC .............................................................................378
BTFSS .............................................................................. 378
BTG .................................................................................. 379
BZ ..................................................................................... 380
C
C Compilers
MPLAB C18 .............................................................416
MPLAB C30 .............................................................416
Calibration (A/D Converter) .............................................. 309
CALL ................................................................................ 380
CALLW .............................................................................409
Capture (CCP Module) ..................................................... 211
Associated Registers ...............................................213
CCPRxH:CCPRxL Registers ................................... 211
CCPx Pin Configuration ...........................................211
Prescaler ..................................................................211
Software Interrupt .................................................... 211
Timer1/Timer3 Mode Selection ................................ 211
Capture (ECCP Module) .................................................. 220
Capture/Compare/PWM (CCP) ........................................ 209
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................ 210
CCPRxH Register .................................................... 210
CCPRxL Register ..................................................... 210
Compare Mode. See Compare.
ECCP/CCP Timer Interconnect Configurations ....... 210
Module Configuration ............................................... 210
Clock Sources .................................................................... 42
Effects of Power-Managed Modes ............................. 46
Selecting the 31 kHz Source ......................................42
Selection Using OSCCON Register ........................... 42
CLRF ................................................................................381
CLRWDT ..........................................................................381
Code Examples
16 x 16 Signed Multiply Routine .............................. 120
16 x 16 Unsigned Multiply Routine .......................... 120
8 x 8 Signed Multiply Routine .................................. 119
8 x 8 Unsigned Multiply Routine .............................. 119
A/D Calibration Routine ...........................................309
Changing Between Capture Prescalers ................... 211
Computed GOTO Using an Offset Value ................... 75
Erasing a Flash Program Memory Row ................... 102
Fast Register Stack .................................................... 75
How to Clear RAM (Bank 1) Using Indirect Addressing .
90
Implementing a Real-Time Clock Using a Timer1 Inter-
rupt Service ...................................................... 199
Initializing PORTA .................................................... 140
Initializing PORTB .................................................... 143
Initializing PORTC .................................................... 146
Initializing PORTD .................................................... 149
Initializing PORTE .................................................... 152
Initializing PORTF ....................................................155
Initializing PORTG ...................................................158
Initializing PORTH .................................................... 161
Initializing PORTJ .................................................... 164
Loading the SSP1BUF (SSP1SR) Register ............. 236
Reading a Flash Program Memory Word ................ 101
Saving STATUS, WREG and BSR Registers in RAM ...
136
Writing to Flash Program Memory ........................... 104
Code Protection ............................................................... 349
COMF .............................................................................. 382
Comparator ...................................................................... 337
Analog Input Connection Considerations ................ 340
Associated Registers ............................................... 344
Configuration ........................................................... 341
Control ..................................................................... 341
Effects of a Reset .................................................... 344
Enable and Input Selection ...................................... 341
Enable and Output Selection ................................... 341
Interrupts ................................................................. 343
Operation ................................................................. 340
Operation During Sleep ........................................... 344
Response Time ........................................................ 340
Comparator Specifications ............................................... 433
Comparator Voltage Reference ....................................... 345
Accuracy and Error .................................................. 347
Associated Registers ............................................... 347
Configuring .............................................................. 346
Connection Considerations ...................................... 347
Effects of a Reset .................................................... 347
Operation During Sleep ........................................... 347
Compare (CCP Module) .................................................. 212
Associated Registers ............................................... 213
CCPRx Register ...................................................... 212
Pin Configuration ..................................................... 212
Software Interrupt .................................................... 212
Timer1/Timer3 Mode Selection ................................ 212
Compare (ECCP Module) ................................................ 220
Special Event Trigger .............................. 205, 220, 308
Computed GOTO ............................................................... 75
Configuration Bits ............................................................ 349
Configuration Mismatch (CM) Reset .................................. 57
Configuration Register Protection .................................... 364
Core Features
Easy Migration ........................................................... 10
Expanded Memory ....................................................... 9
Extended Instruction Set ........................................... 10
External Memory Bus ................................................ 10
nanoWatt Technology .................................................. 9
Oscillator Options and Features .................................. 9
Universal Serial Bus (USB) .......................................... 9
CPFSEQ .......................................................................... 382
CPFSGT .......................................................................... 383
CPFSLT ........................................................................... 383
Crystal Oscillator/Ceramic Resonator ................................ 37
Customer Change Notification Service ............................ 477
Customer Notification Service ......................................... 477
Customer Support ............................................................ 477
D
Data Addressing Modes .................................................... 90
Comparing Addressing Modes with the Extended In-
struction Set Enabled ........................................ 94
Direct ......................................................................... 90
Indexed Literal Offset ................................................ 93
BSR ................................................................... 95
Instructions Affected .......................................... 93
Mapping Access Bank ....................................... 95
Indirect ....................................................................... 90
Inherent and Literal .................................................... 90
Data Memory ..................................................................... 78
Access Bank .............................................................. 80
Bank Select Register (BSR) ...................................... 78
Extended Instruction Set ........................................... 93
General Purpose Registers ....................................... 80
Memory Maps