Datasheet

PIC18F87J50 FAMILY
DS39775C-page 448 © 2009 Microchip Technology Inc.
FIGURE 28-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 28-19: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
SDIx
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note: Refer to Figure 28-3 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
73 T
DIV2SCH,
T
DIV2SCL
Setup Time of SDIx Data Input to SCKx Edge 100 — ns
73A T
B2B Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
1.5 TCY + 40 — ns
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 100 — ns
75 T
DOR SDOx Data Output Rise Time — 25 ns
76 TDOF SDOx Data Output Fall Time — 25 ns
78 T
SCR SCKx Output Rise Time (Master mode) — 25 ns
79 T
SCF SCKx Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx Edge — 50 ns
81 T
DOV2SCH,
T
DOV2SCL
SDOx Data Output Setup to SCKx Edge T
CY —ns