Datasheet

PIC18F87J50 FAMILY
DS39775C-page 442 © 2009 Microchip Technology Inc.
FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
TABLE 28-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 T
MCLMCLR Pulse Width (low) 2 — — μs
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
3.4 4.0 4.6 ms
32 T
OST Oscillator Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period — 65.5 93 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
——3 TCY + 2 μs (Note 1)
38 T
CSD CPU Start-up Time — 200 — μs (Note 2)
Note 1: The maximum T
IOZ is the lesser of (3 TCY + 2 μs) or 400 μs.
2: MCLR
rising edge to code execution, assuming TPWRT (and TOST if applicable) has already expired.
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 28-3 for load conditions.