Datasheet

PIC18F87J50 FAMILY
DS39775C-page 438 © 2009 Microchip Technology Inc.
TABLE 28-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)
TABLE 28-9: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
F10 F
OSC Oscillator Frequency Range 4 — 48 MHz
F11 F
SYS On-Chip VCO System Frequency — 96 — MHz
F12 t
rc
PLL Start-up Time (lock time) — — 2 ms
F13 ΔCLK CLKO Stability (jitter) -0.25 — +0.25 %
† Data in “Typ” column is at 3.3V, 25°C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
Param
No.
Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz,
4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz
(1)
All Devices -2 +/-1 2 % +25°C VDD = 2.7-3.3V
-5 — 5 % -10°C to +85°C VDD = 2.0-3.3V
-10 +/-1 10 % -40°C to +85°C V
DD = 2.0-3.3V
INTRC Accuracy @ Freq = 31 kHz
(1)
All Devices 26.56 — 35.94 kHz -40°C to +85°C VDD = 2.0-3.3V
Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.