Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 437
PIC18F87J50 FAMILY
28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 28-4: EXTERNAL CLOCK TIMING
TABLE 28-7: EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 48 MHz EC Oscillator mode
DC 48 ECPLL Oscillator mode
(2)
Oscillator Frequency
(1)
4 25 MHz HS Oscillator mode
4 25 HSPLL Oscillator mode
(3)
1TOSC External CLKI Period
(1)
20.8 — ns EC Oscillator mode
20.8 — ECPLL Oscillator mode
(2)
Oscillator Period
(1)
40.0 250 ns HS Oscillator mode
40.0 250 HSPLL Oscillator mode
(3)
2TCY Instruction Cycle Time
(1)
83.3 — ns TCY = 4/FOSC, Industrial
3TOSL,
T
OSH
External Clock in (OSC1)
High or Low Time
10 — ns EC Oscillator mode
4TOSR,
T
OSF
External Clock in (OSC1)
Rise or Fall Time
— 7.5 ns EC Oscillator mode
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2: In order to use the PLL, the external clock frequency must be either 4, 8, 12, 16, 20, 24, 40 or 48 MHz.
3: In order to use the PLL, the crystal/resonator must produce a frequency of either 4, 8, 12, 16, 20 or
24 MHz.