Datasheet
PIC18F87J50 FAMILY
DS39775C-page 36 © 2009 Microchip Technology Inc.
2.2.1 OSCILLATOR MODES AND
USB OPERATION
Because of the unique requirements of the USB module,
a different approach to clock operation is necessary. In
order to use the USB module, a fixed 6 MHz or 48 MHz
clock must be internally provided to the USB module for
operation in either Low-Speed or Full-Speed mode,
respectively. The microcontroller core need not be
clocked at the same frequency as the USB module.
A network of MUXes, clock dividers and a fixed 96 MHz
output PLL have been provided which can be used to
derive various microcontroller core and USB module
frequencies. The oscillator structure of the
PIC18F87J50 family of devices is best understood by
referring to Figure 2-1.
FIGURE 2-1: PIC18F87J50 FAMILY CLOCK DIAGRAM
OSC1
OSC2
Primary Oscillator
CPU
Peripherals
IDLE
INTOSC Postscaler
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
111
110
101
100
011
010
001
000
31 kHz
INTRC
31 kHz
Internal
Oscillator
Block
8 MHz
8 MHz
0
1
OSCTUNE<7>
PLLDIV2:PLLDIV0
CPU Divider
÷ 1
÷ 2
÷ 3
÷ 6
USB Module
4 MHz
WDT, PWRT, FSCM
and Two-Speed Start-up
OSCCON<6:4>
PLLEN
1
0
FOSC2
1
0
PLL Prescaler
96 MHz
PLL
(1)
÷ 2
1
0
FSEN
÷ 8
10
11
÷ 4
CPDIV1:CPDIV0
00
01
10
11
CPDIV1:CPDIV0
(Note 2)
00
FOSC2:FOSC1
Other
00
01
OSCCON<1:0>
11
÷ 4
RA6
CLKO
Enabled Modes
Timer1 Clock
(3)
Postscaled
Internal Clock
T1OSI
T1OSO
Secondary Oscillator
T1OSCEN
Clock
Needs 48 MHz for FS
Needs 6 MHz for LS
Note 1: The PLL requires a 4 MHz input and it produces a 96 MHz output. The PLL will not be available until the PLLEN bit
in the OSCTUNE register is set. Once the PLLEN bit is set, the PLL requires up to 2 ms to lock.
2: In order to use the USB module in Full-Speed mode, this node must be run at 48 MHz. For Low-Speed mode, this
node may be run at either 48 MHz or 24 MHz, but the CPDIV bits must be set such that the USB module is clocked
at 6 MHz.
3: Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the
reference clock of Section 2.5 “Reference Clock Output”) and PLL.
4: The USB module cannot be used to communicate unless the primary clock source is selected.
÷ 12
÷ 10
÷ 6
÷ 5
÷ 4
÷ 3
÷ 2
÷ 1
000
001
010
011
100
101
110
111
48 MHz
Primary Clock
Source
(4)