Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 359
PIC18F87J50 FAMILY
TABLE 25-3: SUMMARY OF WATCHDOG TIMER REGISTERS
REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0 R-x U-0 R/W-0 U-0 U-0 U-0 U-0
REGSLP
(2)
LVDSTAT — ADSHR — — —SWDTEN
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit
(2)
1 = On-chip regulator enters low-power operation when device enters Sleep mode
0 = On-chip regulator is active even in Sleep mode
bit 6 LVDSTAT: Low-Voltage Detect Status bit
1 = V
DDCORE > 2.45V nominal
0 = V
DDCORE < 2.45V nominal
bit 5 Unimplemented: Read as ‘0’
bit 4 ADSHR: Shared Address SFR Select bit
For details of bit operation, see Register 5-3.
bit 3-1 Unimplemented: Read as ‘0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
(1)
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Note 1: This bit has no effect if the Configuration bit, WDTEN, is enabled.
2: The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset Values
on Page:
RCON
IPEN — CM RI TO PD POR BOR 62
WDTCON REGSLP LVDSTAT
— ADSHR — — —SWDTEN 63
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.