Datasheet
PIC18F87J50 FAMILY
DS39775C-page 344 © 2009 Microchip Technology Inc.
23.7 Comparator Operation
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
23.8 Effects of a Reset
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
TABLE 23-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR2
OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64
PIE2 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE 64
IPR2
OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP 64
CMxCON CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 62
CVRCON
(1)
CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 65
CMSTAT
— — — — — — COUT2 COUT1 65
ANCON1
(1)
PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — —63
ANCON0
(1)
PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63
PORTA
— —RA5RA4 RA3 RA2 RA1 —65
TRISA — —TRISA5TRISA4 TRISA3 TRISA2 TRISA1 —64
LATA — —LATA5LATA4 LATA3 LATA2 LATA1 LATA0 64
PORTC
RC7 RC6 RC5 RC4 RC3 RFC2 RFC1 RFC0 65
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 64
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64
PORTF RF7 RF6 RF5
RF4 RF3 RF2 — —65
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 — —64
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — —64
PORTH
(2)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 65
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 64
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
2: This register is not implemented on 64-pin devices.