Datasheet
PIC18F87J50 FAMILY
DS39775C-page 34 © 2009 Microchip Technology Inc.
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
ALE
62
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
61
I/O
O
ST
—
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
60
I/O
O
ST
—
Digital I/O.
External memory write low control.
RJ3/WRH
RJ3
WRH
59
I/O
O
ST
—
Digital I/O.
External memory write high control.
RJ4/BA0
RJ4
BA0
39
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
RJ5/CE
RJ5
CE
40
I/O
O
ST
—
Digital I/O
External memory chip enable control.
RJ6/LB
RJ6
LB
41
I/O
O
ST
—
Digital I/O.
External memory low byte control.
RJ7/UB
RJ7
UB
42
I/O
O
ST
—
Digital I/O.
External memory high byte control.
VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.
VDD 32, 48, 71 P — Positive supply for peripheral digital logic and I/O pins.
AV
SS 26 P — Ground reference for analog modules.
AVDD 25 P — Positive supply for analog modules.
ENVREG
24 I ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
12
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator enabled).
V
USB
23 P —
USB voltage input pin.
TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.