Datasheet

PIC18F87J50 FAMILY
DS39775C-page 314 © 2009 Microchip Technology Inc.
REGISTER 22-2: UCFG: USB CONFIGURATION REGISTER
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UTEYE — — UPUEN
(1,2)
UTRDIS
(1)
FSEN
(1)
PPB1 PPB0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6 Unimplemented: Always should be programmed to ‘0’
(3)
bit 5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit
(1,2)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 UTRDIS: On-Chip Transceiver Disable bit
(1)
1 = On-chip transceiver disabled
0 = On-chip transceiver active
bit 2 FSEN: Full-Speed Enable bit
(1)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
2: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.
3: Firmware should never set this bit. Doing so may cause unexpected behavior.