Datasheet

PIC18F87J50 FAMILY
DS39775C-page 304 © 2009 Microchip Technology Inc.
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AV
DD and AVSS), or the voltage level on the
RA3/AN3/VREF+ and RA2/AN2/VREF- pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
Converter, which generates the result via successive
approximation.
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE
bit (ADCON0<1>) is
cleared and A/D Interrupt Flag bit, ADIF, is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset. These registers will contain unknown
data after a Power-on Reset.
The block diagram of the A/D module is shown in
Figure 21-1.
FIGURE 21-1: A/D BLOCK DIAGRAM
(Input Voltage)
VAIN
VREF+
Reference
Voltage
V
DD
(2)
VCFG1:VCFG0
CHS3:CHS0
AN7
AN4
AN3
AN2
AN1
AN0
0111
0100
0011
0010
0001
0000
10-Bit
A/D
VREF-
VSS
(2)
Converter
AN15
(1)
AN14
(1)
AN13
(1)
AN12
(1)
AN11
AN10
1111
1110
1101
1100
1011
1010
Note 1: Channels AN15 through AN12 are not available on 64-pin devices.
2: I/O pins have diode protection to V
DD and VSS.