Datasheet

PIC18F87J50 FAMILY
DS39775C-page 292 © 2009 Microchip Technology Inc.
FIGURE 20-7: ASYNCHRONOUS RECEPTION
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
20.2.4 AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RXx/DTx line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 20-8) and asynchronously if the device is in
Sleep mode (Figure 20-9). The interrupt condition is
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1
PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64
RCSTAx SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63
RCREGx EUSARTx Receive Register 63
TXSTAx
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63
BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Start
bit
bit 7/8
bit 1bit 0 bit 7/8
bit 0
Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RXx (pin)
Rcv Buffer Reg
Rcv Shift Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREGx
Word 2
RCREGx
Stop
bit
Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.