Datasheet

PIC18F87J50 FAMILY
DS39775C-page 290 © 2009 Microchip Technology Inc.
FIGURE 20-4: ASYNCHRONOUS TRANSMISSION
FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREGx
BRG Output
(Shift Clock)
TXx (pin)
TXxIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1
PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1
PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64
RCSTAx
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 63
TXREGx
EUSARTx Transmit Register 63
TXSTAx
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 63
BAUDCONx ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN 65
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 65
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 65
ODCON2
— — — — U2OD U1OD 62
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.