Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 29
PIC18F87J50 FAMILY
PORTE is a bidirectional I/O port (continued).
RE6/AD14/PMA10/P1B
RE6
AD14
PMA10
P1B
(3)
74
I/O
I/O
O
O
ST
TTL
—
—
Digital I/O.
External memory address/data 14.
Parallel Master Port address.
ECCP1 PWM output B.
RE7/AD15/PMA9/
ECCP2/P2A
RE7
AD15
PMA9
ECCP2
(4)
P2A
(4)
73
I/O
I/O
O
I/O
O
ST
TTL
—
ST
—
Digital I/O.
External memory address/data 15.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.