Datasheet

PIC18F87J50 FAMILY
DS39775C-page 28 © 2009 Microchip Technology Inc.
PORTE is a bidirectional I/O port.
RE0/AD8/PMRD/P2D
RE0
AD8
PMRD
(6)
P2D
4
I/O
I/O
I/O
O
ST
TTL
Digital I/O.
External memory address/data 8.
Parallel Master Port read strobe.
ECCP2 PWM output D.
RE1/AD9/PMWR/P2C
RE1
AD9
PMWR
(6)
P2C
3
I/O
I/O
I/O
O
ST
TTL
Digital I/O.
External memory address/data 9.
Parallel Master Port write strobe.
ECCP2 PWM output C.
RE2/AD10/PMBE/P2B
RE2
AD10
PMBE
(6)
P2B
78
I/O
I/O
O
O
ST
TTL
Digital I/O.
External memory address/data 10.
Parallel Master Port byte enable.
ECCP2 PWM output B.
RE3/AD11/PMA13/
P3C/REFO
RE3
AD11
PMA13
P3C
(3)
REFO
77
I/O
I/O
O
O
O
ST
TTL
Digital I/O.
External memory address/data 11.
Parallel Master Port address.
ECCP3 PWM output C.
Reference Clock out.
RE4/AD12/PMA12/P3B
RE4
AD12
PMA12
P3B
(3)
76
I/O
I/O
O
O
ST
TTL
Digital I/O.
External memory address/data 12.
Parallel Master Port address.
ECCP3 PWM output B.
RE5/AD13/PMA11/P1C
RE5
AD13
PMA11
P1C
(3)
75
I/O
I/O
O
O
ST
TTL
Digital I/O.
External memory address/data 13.
Parallel Master Port address.
ECCP1 PWM output C.
TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.