Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 27
PIC18F87J50 FAMILY
PORTD is a bidirectional I/O port (continued).
RD6/AD6/PMD6/
SCK2/SCL2
RD6
AD6
PMD6
(6)
SCK2
SCL2
64
I/O
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
ST
Digital I/O.
External memory address/data 6.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C™ mode.
RD7/AD7/PMD7/SS2
RD7
AD7
PMD7
(6)
SS2
63
I/O
I/O
I/O
I
ST
TTL
TTL
TTL
Digital I/O.
External memory address/data 7.
Parallel Master Port data.
SPI slave select input.
TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.