Datasheet

PIC18F87J50 FAMILY
DS39775C-page 242 © 2009 Microchip Technology Inc.
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR1
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PIR3 SSP2IF
BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 64
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 64
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — —64
SSP1BUF MSSP1 Receive Buffer/Transmit Register 62
SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 62, 65
SSPxSTAT SMP CKE
D/A P S R/W UA BF 62, 65
SSP2BUF MSSP2 Receive Buffer/Transmit Register 65
ODCON3
(1)
— — — — — —SPI2ODSPI1OD62
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.