Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 23
PIC18F87J50 FAMILY
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
30
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
29
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/V
REF-
RA2
AN2
V
REF-
28
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/V
REF+
RA3
AN3
V
REF+
27
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/PMD5/T0CKI
RA4
PMD5
(7)
T0CKI
34
I/O
I/O
I
ST
TTL
ST
Digital I/O.
Parallel Master Port data.
Timer0 external clock input.
RA5/PMD4/AN4/C2INA
RA5
PMD4
(7)
AN4
C2INA
33
I/O
I/O
I
I
TTL
TTL
Analog
Analog
Digital I/O.
Parallel Master Port data.
Analog input 4.
Comparator 2 input A.
RA6
RA7
—
—
—
—
—
—
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.