Datasheet

PIC18F87J50 FAMILY
DS39775C-page 22 © 2009 Microchip Technology Inc.
TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
MCLR
9 I ST Master Clear (Reset) input. This pin is an active-low Reset
to the device.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
(8)
49
I
I
I/O
ST
CMOS
TTL
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS
otherwise.
Main oscillator input connection.
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
Main clock input connection.
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
(8)
50
O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
Main oscillator feedback output connection.
In RC mode, OSC2 pin outputs CLKO which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
System cycle clock output (F
OSC/4).
General purpose I/O pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.