Datasheet

PIC18F87J50 FAMILY
DS39775C-page 216 © 2009 Microchip Technology Inc.
TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
RCON IPEN
— CM RI TO PD POR BOR 62
PIR1
PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 64
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 64
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 64
TMR2
(1)
Timer2 Register 62
PR2
(1)
Timer2 Period Register 62
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 62
TMR4 Timer4 Register 65
PR4
(1)
Timer4 Period Register 65
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 65
CCPR4L Capture/Compare/PWM Register 4 Low Byte 65
CCPR4H Capture/Compare/PWM Register 4 High Byte 65
CCPR5L Capture/Compare/PWM Register 5 Low Byte 65
CCPR5H Capture/Compare/PWM Register 5 High Byte 65
CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 65
CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 65
ODCON1
(2)
— — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2 or Timer4.
Note 1: Default (legacy) SFR at this address, available when WDTCON<4> = 0.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.