Datasheet

PIC18F87J50 FAMILY
DS39775C-page 212 © 2009 Microchip Technology Inc.
17.3 Compare Mode
In Compare mode, the 16-bit CCPRx register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCPx pin
can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remains unchanged (that is, reflects the state of
the I/O latch)
The action on the pin is based on the value of the mode
select bits (CCPxM3:CCPxM0). At the same time, the
interrupt flag bit, CCPxIF, is set.
17.3.1 CCPx PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
17.3.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCPx module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
17.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCPxM3:CCPxM0 = 1010), the corresponding CCPx
pin is not affected. Only a CCP interrupt is generated,
if enabled and the CCPxIE bit is set.
FIGURE 17-3: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP5CON register will force
the RG4 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTB or
PORTC I/O data latch.
CCPR4H CCPR4L
TMR1H TMR1L
Comparator
QS
R
Output
Logic
Set CCP4IF
CCP4 pin
TRIS
CCP4CON<3:0>
Output Enable
TMR3H TMR3L
CCPR5H CCPR5L
Comparator
1
0
T3CCP2
T3CCP1
Set CCP5IF
1
0
Compare
4
Q
S
R
Output
Logic
CCP5 pin
TRIS
CCP5CON<3:0>
Output Enable
4
Match
Compare
Match