Datasheet
© 2009 Microchip Technology Inc. DS39775C-page 21
PIC18F87J50 FAMILY
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
RG0
PMA8
ECCP3
P3A
3
I/O
O
I/O
O
ST
—
—
—
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
4
I/O
O
O
I/O
ST
—
—
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
5
I/O
O
I
I/O
ST
—
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/PMCS1/CCP4/P3D
RG3
PMCS1
CCP4
P3D
6
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/PMCS2/CCP5/P1D
RG4
PMCS2
CCP5
P1D
8
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
V
SS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.
V
DD 26, 38, 57 P — Positive supply for peripheral digital logic and I/O pins.
AVSS 20 P — Ground reference for analog modules.
AVDD 19 P — Positive supply for analog modules.
ENVREG 18 I ST Enable for on-chip voltage regulator.
V
DDCORE/VCAP
VDDCORE
VCAP
10
P
P
—
—
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
V
USB 17 P — USB voltage input pin.
TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.