Datasheet

PIC18F87J50 FAMILY
DS39775C-page 190 © 2009 Microchip Technology Inc.
TABLE 11-3: REGISTERS ASSOCIATED WITH PMP MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61
PIR1 PMPIF
ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64
PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64
IPR1 PMPIP
ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64
PMCONH PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 66
PMCONL CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP 67
PMADDRH
(1)
/ CS2 CS1 Parallel Master Port Address, High Byte 66
PMDOUT1H
(1)
Parallel Port Out Data, High Byte (Buffer 1) 66
PMADDRL
(1)
/ Parallel Master Port Address, Low Byte 66
PMDOUT1L
(1)
Parallel Port Out Data, Low Byte (Buffer 0) 66
PMDOUT2H Parallel Port Out Data, High Byte (Buffer 3) 66
PMDOUT2L Parallel Port Out Data, Low Byte (Buffer 2) 66
PMDIN1H Parallel Port In Data, High Byte (Buffer 1) 66
PMDIN1L Parallel Port In Data, Low Byte (Buffer 0) 66
PMDIN2H Parallel Port In Data, High Byte (Buffer 3) 67
PMDIN2L Parallel Port In Data, Low Byte (Buffer 2) 67
PMMODEH BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 67
PMMODEL WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0 WAITE1 WAITE0 67
PMEH PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 67
PMEL PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 67
PMSTATH IBF IBOV
— — IB3F IB2F IB1F IB0F 67
PMSTATL OBE OBUF
— — OB3E OB2E OB1E OB0E 67
PADCFG1
(2)
— — — — — — — PMPTTL 62
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
Note 1: The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.