Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 19
PIC18F87J50 FAMILY
PORTE is a bidirectional I/O port.
RE0/PMRD/P2D
RE0
PMRD
P2D
2
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port read strobe.
ECCP2 PWM output D.
RE1/PMWR/P2C
RE1
PMWR
P2C
1
I/O
I/O
O
ST
—
—
Digital I/O.
Parallel Master Port write strobe.
ECCP2 PWM output C.
RE2/PMBE/P2B
RE2
PMBE
P2B
64
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port byte enable
ECCP2 PWM output B.
RE3/PMA13/P3C/REFO
RE3
PMA13
P3C
REFO
63
I/O
O
O
O
ST
—
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM output C.
Reference clock out.
RE4/PMA12/P3B
RE4
PMA12
P3B
62
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP3 PWM output B.
RE5/PMA11/P1C
RE5
PMA11
P1C
61
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM output C.
RE6/PMA10/P1B
RE6
PMA10
P1B
60
I/O
O
O
ST
—
—
Digital I/O.
Parallel Master Port address.
ECCP1 PWM output B.
RE7/PMA9/ECCP2/P2A
RE7
PMA9
ECCP2
(2)
P2A
(2)
59
I/O
O
I/O
O
ST
—
ST
—
Digital I/O.
Parallel Master Port address.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.