Datasheet

PIC18F87J50 FAMILY
DS39775C-page 188 © 2009 Microchip Technology Inc.
11.4 Application Examples
This section introduces some potential applications for
the PMP module.
11.4.1 MULTIPLEXED MEMORY OR
PERIPHERAL
Figure 11-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
FIGURE 11-27: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
11.4.2 PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 shows an example of a mem-
ory or peripheral that is partially multiplexed with an
external latch. If the peripheral has internal latches, as
shown in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
FIGURE 11-29: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
PMD<7:0>
PMALH
D<7:0>
373
A<15:0>
D<7:0>
A<7:0>
373
PMRD
PMWR
OE
WR
CE
PIC18F
Address Bus
Data Bus
Control Lines
PMCS
PMALL
A<15:8>
PMA<14:7>
D<7:0>
373
A<14:0>
D<7:0>
A<7:0>
PMRD
PMWR
OE
WR
CE
PIC18F
Address Bus
Data Bus
Control Lines
PMCS
PMALL
A<14:8>
PMD<7:0>
ALE
PMRD
PMWR
RD
WR
CS
PIC18F
Address Bus
Data Bus
Control Lines
PMCS
PMALL
AD<7:0>
Parallel Peripheral
PMD<7:0>