Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 181
PIC18F87J50 FAMILY
FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE
STROBES, TWO CHIP SELECTS)
FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND
WRITE STROBES, TWO CHIP SELECTS)
FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE
STROBES, TWO CHIP SELECTS)
PMRD
PMWR
PMD<7:0>
PMCS1
PMA<13:0>
PMCS2
PIC18F
Address Bus
Data Bus
Control Lines
PMRD
PMWR
PMD<7:0>
PMCS1
PMA<13:8>
PMALL
PMA<7:0>
PMCS2
PIC18F
Address Bus
Multiplexed
Data and
Address Bus
Control Lines
PMRD
PMWR
PMD<7:0>
PMCS1
PMALH
PMA<13:8>
PMCS2
PIC18F
Multiplexed
Data and
Address Bus
Control Lines
PMALL