Datasheet

PIC18F87J50 FAMILY
DS39775C-page 18 © 2009 Microchip Technology Inc.
PORTD is a bidirectional I/O port.
RD0/PMD0
RD0
PMD0
58
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
RD1/PMD1
RD1
PMD1
55
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
RD2/PMD2
RD2
PMD2
54
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
RD3/PMD3
RD3
PMD3
53
I/O
I/O
ST
TTL
Digital I/O.
Parallel Master Port data.
RD4/PMD4/SDO2
RD4
PMD4
SDO2
52
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Master Port data.
SPI data out.
RD5/PMD5/SDI2/SDA2
RD5
PMD5
SDI2
SDA2
51
I/O
I/O
I
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Master Port data.
SPI data in.
I
2
C™ data I/O.
RD6/PMD6/SCK2/SCL2
RD6
PMD6
SCK2
SCL2
50
I/O
I/O
I/O
I/O
ST
TTL
ST
ST
Digital I/O.
Parallel Master Port data.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
2
C mode.
RD7/PMD7/SS2
RD7
PMD7
SS2
49
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Master Port data.
SPI slave select input.
TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to V
DD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.