Datasheet

PIC18F87J50 FAMILY
DS39775C-page 162 © 2009 Microchip Technology Inc.
TABLE 10-18: PORTH FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RH0/A16 RH0 0 O DIG LATH<0> data output.
1 I ST PORTH<0> data input.
A16 x O DIG External memory interface, address line 16. Takes priority over port data.
RH1/A17 RH1 0 O DIG LATH<1> data output.
1 I ST PORTH<1> data input.
A17 x O DIG External memory interface, address line 17. Takes priority over port data.
RH2/A18/
PMD7
RH2 0 O DIG LATH<2> data output.
1 I ST PORTH<2> data input.
A18 x O DIG External memory interface, address line 18. Takes priority over port data.
PMD7
(2)
x O DIG Parallel Master Port data out.
x I TTL Parallel Master Port data input.
RH3/A19/
PMD6
RH3 0 O DIG LATH<3> data output.
1 I ST PORTH<3> data input.
A19 x O DIG External memory interface, address line 19. Takes priority over port data.
PMD6
(2)
x O DIG Parallel Master Port data out.
x I TTL Parallel Master Port data input.
RH4/PMD3/
AN12/P3C/
C2INC
RH4 0 O DIG LATH<4> data output.
1 I ST PORTH<4> data input.
PMD3
(2)
X I TTL Parallel Master Port data out.
X O DIG Parallel Master Port data input.
AN12 I ANA A/D input channel 12. Default input configuration on POR; does not affect
digital output.
P3C
(1)
0 O DIG ECCP3 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2INC x I ANA Comparator 2 input C.
RH5/PMBE/
AN13/P3B/
C2IND
RH5 0 O DIG LATH<5> data output.
1 I ST PORTH<5> data input.
PMBE
(2)
x O DIG Parallel Master Port Data byte enable.
AN13 I ANA A/D input channel 13. Default input configuration on POR; does not affect
digital output.
P3B
(1)
0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C2IND x I ANA Comparator 2 input D.
RH6/PMRD/
AN14/P1C/
C1INC
RH6 0 O DIG LATH<6> data output.
1 I ST PORTH<6> data input.
PMRD
(2)
x O DIG Parallel Master Port read strobe.
x I TTL Parallel Master Port read in.
AN14 I ANA A/D input channel 14. Default input configuration on POR; does not affect
digital output.
P1C
(1)
0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP
data. May be configured for tri-state during Enhanced PWM shutdown events.
C1INC x I ANA Comparator 1 input C.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is cleared. Default assignments are
PORTE<6:3>.
2: When PMPMX = 0.