Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 153
PIC18F87J50 FAMILY
TABLE 10-12: PORTE FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AD8/
PMRD/P2D
RE0 0 O DIG LATE<0> data output.
1 I ST PORTE<0> data input.
AD8
(3)
x O DIG External memory interface, address/data bit 8 output.
(2)
x I TTL External memory interface, data bit 8 input.
(2)
PMRD
(5)
x O DIG Parallel Master Port read strobe pin.
x I TTL Parallel Master Port read pin.
P2D 0 O DIG ECCP2 Enhanced PWM output, channel D; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE1/AD9/
PMWR/P2C
RE1 0 O DIG LATE<1> data output.
1 I ST PORTE<1> data input.
AD9
(3)
x O DIG External memory interface, address/data bit 9 output.
(2)
x I TTL External memory interface, data bit 9 input.
(2)
PMWR
(5)
x O DIG Parallel Master Port write strobe pin.
x I TTL Parallel Master Port write pin.
P2C 0 O DIG ECCP2 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE2/AD10/
PMBE/P2B
RE2 0 O DIG LATE<2> data output.
1 I ST PORTE<2> data input.
AD10
(3)
x O DIG External memory interface, address/data bit 10 output.
(2)
x I TTL External memory interface, data bit 10 input.
(2)
PMBE
(5)
x O DIG Parallel Master Port byte enable.
P2B 0 O DIG ECCP2 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
RE3/AD11/
PMA13/P3C/
REFO
RE3 0 O DIG LATE<3> data output.
1 I ST PORTE<3> data input.
AD11
(3)
x O DIG External memory interface, address/data bit 11 output.
(2)
x I TTL External memory interface, data bit 11 input.
(2)
PMA13 x O DIG Parallel Master Port address.
P3C
(1)
0 O DIG ECCP3 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
REFO x O DIG Reference output clock.
RE4/AD12/
PMA12/P3B
RE4 0 O DIG LATE<4> data output.
1 I ST PORTE<4> data input.
AD12
(3)
x O DIG External memory interface, address/data bit 12 output.
(2)
x I TTL External memory interface, data bit 12 input.
(2)
PMA12 x O DIG Parallel Master Port address.
P3B
(1)
0 O DIG ECCP3 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
2: External memory interface I/O takes priority over all other digital and PMP I/O.
3: Available on 80-pin devices only.
4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller
mode).
5: Default configuration for PMP (PMPMX Configuration bit = 1).