Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 149
PIC18F87J50 FAMILY
10.5 PORTD, TRISD and
LATD Registers
PORTD is an 8-bit wide, bidirectional port. All pins on
PORTD are digital only and tolerate voltages up to
5.5V.
All pins on PORTD are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output.
On 80-pin devices, PORTD is multiplexed with the
system bus as part of the external memory interface.
I/O port and other functions are only available when the
interface is disabled by setting the EBDIS bit
(MEMCON<7>). When the interface is enabled,
PORTD is the low-order byte of the multiplexed
address/data bus (AD7:AD0). The TRISD bits are also
overridden.
PORTD can also be configured to function as an 8-bit
wide Parallel Master Port data. In this mode, Parallel
Master Port takes priority over the other digital I/O (but
not the external memory interface). This multiplexing is
available when PMPMX = 1. When the Parallel Master
Port is active, the input buffers are TTL. For more
information, refer to Section 11.0 “Parallel Master
Port”
Each of the PORTD pins has a weak internal pull-up.
The pull-ups are provided to keep the inputs at a known
state for the external memory interface while powering
up. A single control bit can turn off all the pull-ups. This
is performed by clearing bit, RDPU (PORTG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on all device Resets.
EXAMPLE 10-4: INITIALIZING PORTD
Note: These pins are configured as digital inputs
on any device Reset.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method to clear
; output data latches
MOVLW 0CFh ; Value used to initialize
; data direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs