Datasheet

PIC18F87J50 FAMILY
DS39775C-page 144 © 2009 Microchip Technology Inc.
TABLE 10-6: PORTB FUNCTIONS
Pin Name Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/FLT0/INT0 RB0 0 O DIG LATB<0> data output.
1 I TTL PORTB<0> data input; weak pull-up when RBPU
bit is cleared.
FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software.
INT0 1 I ST External interrupt 0 input.
RB1/INT1/
PMA4
RB1 0 O DIG LATB<1> data output.
1 I TTL PORTB<1> data input; weak pull-up when RBPU
bit is cleared.
INT1 1 I ST External interrupt 1 input.
PMA4 x O — Parallel Master Port address out.
RB2/INT2/
PMA3
RB2 0 O DIG LATB<2> data output.
1 I TTL PORTB<2> data input; weak pull-up when RBPU
bit is cleared.
INT2 1 I ST External interrupt 2 input.
PMA3 x O — Parallel Master Port address out.
RB3/INT3/
ECCP2/P2A/
PMA2
RB3 0 O DIG LATB<3> data output.
1 I TTL PORTB<3> data input; weak pull-up when RBPU
bit is cleared.
INT3 1 I ST External interrupt 3 input.
ECCP2
(1)
0 O DIG ECCP2 compare output and ECCP2 PWM output; takes priority over port
data.
1 I ST ECCP2 capture input.
P2A
(1)
0 O DIG ECCP2 Enhanced PWM output, channel A. May be configured for tri-state
during Enhanced PWM shutdown events. Takes priority over port data.
PMA2 x O — Parallel Master Port address out.
RB4/KBI0/
PMA1
RB4 0 O DIG LATB<4> data output.
1 I TTL PORTB<4> data input; weak pull-up when RBPU
bit is cleared.
KBI0 I TTL Interrupt-on-pin change.
PMA1 x O — Parallel Master Port address out.
RB5/KBI1/
PMA0
RB5 0 O DIG LATB<5> data output.
1 I TTL PORTB<5> data input; weak pull-up when RBPU
bit is cleared.
KBI1 I TTL Interrupt-on-pin change.
PMA0 x O — Parallel Master Port address out.
RB6/KBI2/PGC RB6 0 O DIG LATB<6> data output.
1 I TTL PORTB<6> data input; weak pull-up when RBPU
bit is cleared.
KBI2 1 I TTL Interrupt-on-pin change.
PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.
(2)
RB7/KBI3/PGD RB7 0 O DIG LATB<7> data output.
1 I TTL PORTB<7> data input; weak pull-up when RBPU
bit is cleared.
KBI3 1 I TTL Interrupt-on-pin change.
PGD x O DIG Serial execution data output for ICSP and ICD operation.
(2)
x I ST Serial execution data input for ICSP and ICD operation.
(2)
Legend: O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode,
80-pin devices only). Default assignment is RC1.
2: All other pin functions are disabled when ICSP™ or ICD are enabled.