Datasheet

PIC18F87J50 FAMILY
DS39775C-page 140 © 2009 Microchip Technology Inc.
10.2 PORTA, TRISA and
LATA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. The
corresponding Output Latch register is LATA.
The RA4 pin is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. It is also multi-
plexed as the Parallel Master Port Data pin. The other
PORTA pins are multiplexed with the analog V
REF+ and
V
REF- inputs. The operation of pins RA5:RA0 as A/D
Converter inputs is selected by clearing or setting the
control bits in the ANCON0 register.
The RA4/T0CKI pin is a Schmitt Trigger input. All other
PORTA pins have TTL input levels and full CMOS
output drivers.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally
serve as the external circuit connections for the
external (primary) oscillator circuit (HS and HSPLL
Oscillator modes), or the external clock input (EC and
ECPLL Oscillator modes). In these cases, RA6 and
RA7 are not available as digital I/O and their
corresponding TRIS and LAT bits are read as ‘0’.
For INTOSCx and INTOSCPLLx Oscillator modes
(FOSC2 Configuration bit is ‘0’), either RA7, or both
RA6 and RA7, automatically become available as digi-
tal I/O, depending on the oscillator mode selected.
When RA6 is not configured as a digital I/O, in these
cases, it provides a clock output at F
OSC/4. A list of the
possible configurations for RA6 and RA7, based on
oscillator mode, is provided in Register 10-3. For these
pins, the corresponding PORTA, TRISA and LATA bits
are only defined when the pins are configured as I/O.
TABLE 10-3: FUNCTION OF RA7:RA6 IN
INTOSC AND INTOSCPLL
MODES
EXAMPLE 10-1: INITIALIZING PORTA
REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —PMPTTL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 Unimplemented: Read as ‘0’
bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffers
Note 1: The RA5 (RA5/PMD4/AN4/C2INA) pin is a
multiplexed A/D convertor, Parallel Master
Port data and also a Comparator 2 input A.
(PMP pin placement depends on the
PMPMX Configuration bit.)
2: RA5 and RA3:RA0 are configured as
analog inputs on any Reset and are read
as ‘0’. RA4 is configured as a digital input.
Oscillator Mode
(FOSC2:FOSC0 Configuration bits)
RA6 RA7
INTOSCPLLO (011) CLKO I/O
INTOSCPLL (010) I/O I/O
INTOSCO (001) CLKO I/O
INTOSC (000) I/O I/O
Legend: CLKO = F
OSC/4 clock output; I/O = digital
port.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method to
; clear data latches
BSF WDTCON,ADSHR ; Enable write/read to
; the shared SFR
MOVLW 1Fh ; Configure A/D
MOVWF ANCON0 ; for digital inputs
BCF WDTCON,ADSHR ; Disable write/read
; to the shared SFR
MOVLW 0CFh ; Value used to
; initialize
; data direction
MOVWF TRISA ; Set RA<3:0> as inputs,
; RA<5:4> as outputs