Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 139
PIC18F87J50 FAMILY
REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — —
CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’
bit 4-3 CCP5OD:CCP4OD: CCPx Open-Drain Output Enable bits
1 = Open-drain output on CCPx pin (Capture/PWM modes) enabled
0 = Open-drain output disabled
bit 2-0 ECCP3OD:ECCP1OD: ECCPx Open-Drain Output Enable bits
1 = Open-drain output on ECCPx pin (Capture mode) enabled
0 = Open-drain output disabled
REGISTER 10-2: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — —
U2OD U1OD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 U2OD:U1OD: EUSARTx Open-Drain Output Enable bits
1 = Open-drain output on TXx/CKx pin enabled
0 = Open-drain output disabled
REGISTER 10-3: ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — —
SPI2OD SPI1OD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1-0 SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits
1 = Open-drain output on SDOx pin enabled
0 = Open-drain output disabled