Datasheet

© 2009 Microchip Technology Inc. DS39775C-page 137
PIC18F87J50 FAMILY
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to nine ports available. Some
pins of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three memory-mapped registers for its
operation:
• TRIS register (Data Direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (Output Latch register)
Reading the PORT register reads the current status of
the pins, whereas writing to the PORT register writes to
the output latch (LAT) register.
Setting a TRIS bit (= 1) makes the corresponding
PORT pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRIS bit
(= 0) makes the corresponding PORT pin an output
(i.e., put the contents of the corresponding LAT bit on
the selected pin).
The Data Latch (LAT register) is useful for
read-modify-write operations on the value that the I/O
pins are driving. Read-modify-write operations on the
LAT register read and write the latched output value for
PORT register.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 I/O Port Pin Capabilities
When developing an application, the capabilities of the
port pins must be considered. Outputs on some pins
have higher output drive strength than others. Similarly,
some pins can tolerate higher than V
DD input levels.
10.1.1 INPUT PINS AND VOLTAGE
CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Pins that are used
as digital only inputs are able to handle DC voltages up
to 5.5V, a level typical for digital logic circuits. In contrast,
pins that also have analog input functions of any kind
(such as A/D and comparator inputs) can only tolerate
voltages up to V
DD. Voltage excursions beyond VDD on
these pins should be avoided.
Table 10-1 summarizes the input capabilities. Refer to
Section 28.0 “Electrical Characteristics” for more
details.
TABLE 10-1: INPUT VOLTAGE LEVELS
10.1.2 PIN OUTPUT DRIVE
When used as digital I/O, the output pin drive strengths
vary for groups of pins intended to meet the needs for
a variety of applications. In general, there are three
classes of output pins in terms of drive capability.
PORTB and PORTC, as well as PORTA<7:6>, are
designed to drive higher current loads, such as LEDs.
PORTD, PORTE and PORTJ are capable of driving
digital circuits associated with external memory
devices. They can also drive LEDs, but only those with
smaller current requirements. PORTF, PORTG and
PORTH, along with PORTA<5:0>, have the lowest
drive level, but are capable of driving normal digital
circuit loads with a high input impedance.
Data
Bus
WR LAT
WR TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin
QD
CK
QD
CK
EN
QD
EN
RD LAT
or PORT
Port or Pin
Tolerated
Input
Description
PORTA<5:0> V
DD Only VDD input levels
tolerated.
PORTC<1:0>
PORTF<6:1>
PORTH<7:4>
(1)
PORTB<7:0> 5.5V Tolerates input levels
above V
DD, useful for
most standard logic.
PORTC<7:2>
PORTD<7:0>
PORTE<7:0>
PORTF<7>
PORTG<4:0>
PORTH<3:0>
(1)
PORTJ<7:0>
(1)
Note 1: These ports are not available on 64-pin
devices.