PIC18F87J50 Family Data Sheet 64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F87J50 FAMILY 64/80-Pin High-Performance, 1-Mbit Flash USB Microcontrollers with nanoWatt Technology Universal Serial Bus Features: Peripheral Highlights (continued): • USB V2.0 Compliant SIE • Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s) • Supports Control, Interrupt, Isochronous and Bulk Transfers • Supports up to 32 Endpoints (16 bidirectional) • 3.
SPI Master I2C™ EUSART Comparators Timers 8/16-Bit External Bus PMP/PSP PIC18F87J50 FAMILY 2 Y Y 2 2 2/3 N Y 2 Y Y 2 2 2/3 N Y 2/3 2 Y Y 2 2 2/3 N Y 8 2/3 2 Y Y 2 2 2/3 N Y 65 12 2/3 2 Y Y 2 2 2/3 Y Y 65 12 2/3 2 Y Y 2 2 2/3 Y Y 3904* 65 12 2/3 2 Y Y 2 2 2/3 Y Y 3904* 65 12 2/3 2 Y Y 2 2 2/3 Y Y MSSP Device Flash Program Memory (bytes) SRAM Data Memory (bytes) PIC18F65J50 32K PIC18F66J50 64K PIC18F66J55 I/O 10-
PIC18F87J50 FAMILY Note RJ0/ALE RJ1/OE 61 RD3/AD3/PMD3(3) 67 62 RD2/AD2/PMD2(3) 68 RD7/AD7/PMD7(3)/SS2 RD1/AD1/PMD1(3) 69 63 VSS 70 RD6/AD6/PMD6(3)/SCK2/SCL2 VDD 71 64 RD0/AD0/PMD0 72 RD4/AD4/PMD4(3)/SDO2 RE7/AD15/PMA9/ECCP2(1)/P2A(1) 73 RD5/AD5/PMD5(3)/SDI2/SDA2 RE6/AD14/PMA10/P1B(2) 74 65 RE5/AD13/PMA11/P1C(2) 75 66 RE3/AD11/PMA13/P3C(2)/REFO RE4/AD12/PMA12/P3B(2) RE2/AD10/PMBE(3)/P2B PIC18F8XJ5X 51 50 49 48 47 46 45 44 17 18 19 20 26 27 28 29 30 31 32 33 34 35 36 37
PIC18F87J50 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Configurations ............................................................................................................................................................ 35 3.0 Power-Managed Modes ....................................................................
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PIC18F87J50 FAMILY NOTES: DS39775C-page 8 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F65J50 • PIC18F85J50 • PIC18F66J50 • PIC18F86J50 • PIC18F66J55 • PIC18F86J55 • PIC18F67J50 • PIC18F87J50 This family introduces a new line of low-voltage USB microcontrollers with the main traditional advantage of all PIC18 microcontrollers – namely, high computational performance and a rich feature set – at an extremely competitive price point.
PIC18F87J50 FAMILY 1.1.5 EXTERNAL MEMORY BUS In the event that 128 Kbytes of memory are inadequate for an application, the 80-pin members of the PIC18F87J10 family also implement an External Memory Bus (EMB). This allows the controller’s internal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim.
PIC18F87J50 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F6XJ5X (64-PIN DEVICES) Features PIC18F65J50 PIC18F66J50 PIC18F66J55 PIC18F67J50 DC – 48 MHz DC – 48 MHz DC – 48 MHz DC – 48 MHz 32K 64K 96K 128K Program Memory (Instructions) 16384 32768 49152 65536 Data Memory (Bytes) 3904 3904 3904 3904 Operating Frequency Program Memory (Bytes) Interrupt Sources 30 I/O Ports Ports A, B, C, D, E, F, G Timers 5 Capture/Compare/PWM Modules 2 Enhanced Capture/ Compare/PWM Modules 3
PIC18F87J50 FAMILY FIGURE 1-1: PIC18F6XJ5X (64-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> 20 Address Latch PCU PCH PCL Program Counter 12 Data Address<12> 31 Level Stack 4 BSR Address Latch STKPTR Program Memory (32-128 Kbytes) 12 PORTC RC0:RC7(1) inc/dec logic Table Latch Address Decode ROM Latch Instruction Bus <16> PORTB RB0:RB7(1) 4 Access Bank 12 FSR0 FSR1 FSR2 Data Latch 8 RA0:RA5(1) Data Memory (3.
PIC18F87J50 FAMILY FIGURE 1-2: PIC18F8XJ5X (80-PIN) BLOCK DIAGRAM Data Bus<8> Table Pointer<21> inc/dec logic 21 31 Level Stack Address Latch System Bus Interface Address Latch PCU PCH PCL Program Counter PORTB RB0:RB7(1) 12 Data Address<12> 4 4 12 BSR STKPTR Program Memory (32-128 Kbytes) RA0:RA5(1) Data Memory (3.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS Pin Number 64-TQFP Pin Type Buffer Type MCLR 7 I ST OSC1/CLKI/RA7 OSC1 39 Pin Name I CLKI I RA7(3) OSC2/CLKO/RA6 OSC2 I/O Description Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS Main oscillator input connection.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 24 RA1/AN1 RA1 AN1 23 RA2/AN2/VREFRA2 AN2 VREF- 22 RA3/AN3/VREF+ RA3 AN3 VREF+ 21 RA4/T0CKI RA4 T0CKI 28 RA5/AN4/C2INA RA5 AN4 C2INA 27 RA6 RA7 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I TTL Analog Analog Digital I/O. Analog input 2.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 30 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(1) P2A(1) 29 RC2/ECCP1/P1A RC2 ECCP1 P1A 33 RC3/SCK1/SCL1 RC3 SCK1 SCL1 34 RC4/SDI1/SDA1 RC4 SDI1 SDA1 35 RC5/SDO1/C2OUT RC5 SDO1 C2OUT 36 RC6/TX1/CK1 RC6 TX1 CK1 31 RC7/RX1/DT1 RC7 RX1 DT1 32 I/O O I ST — ST Digital I/O.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/PMD0 RD0 PMD0 58 RD1/PMD1 RD1 PMD1 55 RD2/PMD2 RD2 PMD2 54 RD3/PMD3 RD3 PMD3 53 RD4/PMD4/SDO2 RD4 PMD4 SDO2 52 RD5/PMD5/SDI2/SDA2 RD5 PMD5 SDI2 SDA2 51 RD6/PMD6/SCK2/SCL2 RD6 PMD6 SCK2 SCL2 50 RD7/PMD7/SS2 RD7 PMD7 SS2 49 I/O I/O ST TTL Digital I/O. Parallel Master Port data. I/O I/O ST TTL Digital I/O.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/PMRD/P2D RE0 PMRD P2D 2 RE1/PMWR/P2C RE1 PMWR P2C 1 RE2/PMBE/P2B RE2 PMBE P2B 64 RE3/PMA13/P3C/REFO RE3 PMA13 P3C REFO 63 RE4/PMA12/P3B RE4 PMA12 P3B 62 RE5/PMA11/P1C RE5 PMA11 P1C 61 RE6/PMA10/P1B RE6 PMA10 P1B 60 RE7/PMA9/ECCP2/P2A RE7 PMA9 ECCP2(2) P2A(2) 59 I/O I/O O ST — — Digital I/O.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF2/PMA5/AN7/C2INB RF2 PMA5 AN7 C2INB 16 RF3/DRF3 D- 15 RF4/D+ RF4 D+ 14 RF5/AN10/C1INB/CVREF RF5 AN10 C1INB CVREF 13 RF6/AN11/C1INA RF6 AN11 C1INA 12 RF7/SS1/C1OUT RF7 SS1 C1OUT 11 I/O O I I ST — Analog Analog Digital I/O. Parallel Master Port address. Analog input 7. Comparator 2 input B.
PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 64-TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/PMA8/ECCP3/P3A RG0 PMA8 ECCP3 P3A 3 RG1/PMA7/TX2/CK2 RG1 PMA7 TX2 CK2 4 RG2/PMA6/RX2/DT2 RG2 PMA6 RX2 DT2 5 RG3/PMCS1/CCP4/P3D RG3 PMCS1 CCP4 P3D 6 RG4/PMCS2/CCP5/P1D RG4 PMCS2 CCP5 P1D 8 VSS 9, 25, 41, 56 I/O O I/O O ST — — — Digital I/O. Parallel Master Port address.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS Pin Number 80-TQFP Pin Type Buffer Type MCLR 9 I ST OSC1/CLKI/RA7 OSC1 49 Pin Name I I CLKI RA7(8) OSC2/CLKO/RA6 OSC2 I/O Description Master Clear (Reset) input. This pin is an active-low Reset to the device. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. CMOS Main oscillator input connection.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 RA1/AN1 RA1 AN1 29 RA2/AN2/VREFRA2 AN2 VREF- 28 RA3/AN3/VREF+ RA3 AN3 VREF+ 27 RA4/PMD5/T0CKI RA4 PMD5(7) T0CKI 34 RA5/PMD4/AN4/C2INA RA5 PMD4(7) AN4 C2INA 33 RA6 RA7 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T13CKI RC0 T1OSO T13CKI 36 RC1/T1OSI/ECCP2/P2A RC1 T1OSI ECCP2(2) P2A(2) 35 RC2/ECCP1/P1A RC2 ECCP1 P1A 43 RC3/SCK1/SCL1 RC3 SCK1 SCL1 44 RC4/SDI1/SDA1 RC4 SDI1 SDA1 45 RC5/SDO1/C2OUT RC5 SDO1 C2OUT 46 RC6/TX1/CK1 RC6 TX1 CK1 37 RC7/RX1/DT1 RC7 RX1 DT1 38 I/O O I ST — ST Digital I/O.
PIC18F87J50 FAMILY TABLE 1-4: Pin Name PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 80-TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port. RD0/AD0/PMD0 RD0 AD0 PMD0(6) 72 RD1/AD1/PMD1 RD1 AD1 PMD1(6) 69 RD2/AD2/PMD2 RD2 AD2 PMD2(6) 68 RD3/AD3/PMD3 RD3 AD3 PMD3(6) 67 RD4/AD4/PMD4/ SDO2 RD4 AD4 PMD4(6) SDO2 66 RD5/AD5/PMD5/ SDI2/SDA2 RD5 AD5 PMD5(6) SDI2 SDA2 65 I/O I/O I/O ST TTL TTL Digital I/O. External memory address/data 0. Parallel Master Port data.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTD is a bidirectional I/O port (continued). RD6/AD6/PMD6/ SCK2/SCL2 RD6 AD6 PMD6(6) SCK2 SCL2 64 RD7/AD7/PMD7/SS2 RD7 AD7 PMD7(6) SS2 63 I/O I/O I/O I/O I/O ST TTL TTL ST ST Digital I/O. External memory address/data 6. Parallel Master Port data. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C™ mode.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port. RE0/AD8/PMRD/P2D RE0 AD8 PMRD(6) P2D 4 RE1/AD9/PMWR/P2C RE1 AD9 PMWR(6) P2C 3 RE2/AD10/PMBE/P2B RE2 AD10 PMBE(6) P2B 78 RE3/AD11/PMA13/ P3C/REFO RE3 AD11 PMA13 P3C(3) REFO 77 RE4/AD12/PMA12/P3B RE4 AD12 PMA12 P3B(3) 76 RE5/AD13/PMA11/P1C RE5 AD13 PMA11 P1C(3) 75 I/O I/O I/O O ST TTL — — Digital I/O.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTE is a bidirectional I/O port (continued). RE6/AD14/PMA10/P1B RE6 AD14 PMA10 P1B(3) 74 RE7/AD15/PMA9/ ECCP2/P2A RE7 AD15 PMA9 ECCP2(4) P2A(4) 73 I/O I/O O O ST TTL — — Digital I/O. External memory address/data 14. Parallel Master Port address. ECCP1 PWM output B. I/O I/O O I/O O ST TTL — ST — Digital I/O. External memory address/data 15.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTF is a bidirectional I/O port. RF2/PMA5/AN7/C2INB RF2 PMA5 AN7 C2INB 18 RF3/DRF3 D- 17 RF4/D+ RF4 D+ 16 RF5/PMD2/AN10/ C1INB/CVREF RF5 PMD2(7) AN10 C1INB CVREF 15 RF6/PMD1/AN11/C1INA RF6 PMD1(7) AN11 C1INA 14 RF7/PMD0/SS1/C1OUT RF7 PMD0(7) SS1 C1OUT 13 I/O O I I ST — Analog Analog Digital I/O. Parallel Master Port address. Analog input 7.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTG is a bidirectional I/O port. RG0/PMA8/ECCP3/P3A RG0 PMA8 ECCP3 P3A 5 RG1/PMA7/TX2/CK2 RG1 PMA7 TX2 CK2 6 RG2/PMA6/RX2/DT2 RG2 PMA6 RX2 DT2 7 RG3/PMCS1/CCP4/P3D RG3 PMCS1 CCP4 P3D 8 RG4/PMCS2/CCP5/P1D RG4 PMCS2 CCP5 P1D 10 I/O O I/O O ST — ST — Digital I/O. Parallel Master Port address. Capture 3 input/Compare 3 output/PWM3 output.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port. RH0/A16 RH0 A16 79 RH1/A17 RH1 A17 80 RH2/A18/PMD7 RH2 A18 PMD7(7) 1 RH3/A19/PMD6 RH3 A19 PMD6(7) 2 RH4/PMD3/AN12/ P3C/C2INC RH4 PMD3(7) AN12 P3C(5) C2INC 22 RH5/PMBE/AN13/ P3B/C2IND RH5 PMBE(7) AN13 P3B(5) C2IND 21 RH6/PMRD/AN14/ P1C/C1INC RH6 PMRD(7) AN14 P1C(5) C1INC 20 I/O O ST TTL Digital I/O.
PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number 80-TQFP Pin Type Buffer Type Description PORTH is a bidirectional I/O port (continued). RH7/PMWR/AN15/P1B RH7 PMWR(7) AN15 P1B(5) 19 I/O I/O I O ST — Analog — Digital I/O. Parallel Master Port write strobe. Analog input 15. ECCP1 PWM output B.
PIC18F87J50 FAMILY TABLE 1-4: Pin Name PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number 80-TQFP Pin Type Buffer Type Description PORTJ is a bidirectional I/O port. RJ0/ALE RJ0 ALE 62 RJ1/OE RJ1 OE 61 RJ2/WRL RJ2 WRL 60 RJ3/WRH RJ3 WRH 59 RJ4/BA0 RJ4 BA0 39 RJ5/CE RJ5 CE 40 RJ6/LB RJ6 LB 41 RJ7/UB RJ7 UB 42 VSS 11, 31, 51, 70 I/O O ST — Digital I/O. External memory address latch enable. I/O O ST — Digital I/O. External memory output enable. I/O O ST — Digital I/O.
PIC18F87J50 FAMILY 2.0 2.1 OSCILLATOR CONFIGURATIONS Overview Devices in the PIC18F87J10 family incorporate a different oscillator and microcontroller clock system than general purpose PIC18F devices. The addition of the USB module, with its unique requirements for a stable clock source, make it necessary to provide a separate clock source that is compliant with both USB low-speed and full-speed specifications.
PIC18F87J50 FAMILY 2.2.1 OSCILLATOR MODES AND USB OPERATION A network of MUXes, clock dividers and a fixed 96 MHz output PLL have been provided which can be used to derive various microcontroller core and USB module frequencies. The oscillator structure of the PIC18F87J50 family of devices is best understood by referring to Figure 2-1. Because of the unique requirements of the USB module, a different approach to clock operation is necessary.
PIC18F87J50 FAMILY 2.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS In HS and HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-2 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications.
PIC18F87J50 FAMILY FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from Ext. System PIC18F87J50 Open 2.2.3 OSC2 (HS Mode) EXTERNAL CLOCK INPUT The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC and ECPLL Oscillator modes, the oscillator frequency divided by 4 is available on the OSC2 pin.
PIC18F87J50 FAMILY 2.2.5.1 OSCTUNE Register The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately, 8 * 32 μs = 256 μs).
PIC18F87J50 FAMILY REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F87J50 FAMILY TABLE 2-5: OSCILLATOR CONFIGURATION OPTIONS FOR USB OPERATION Input Oscillator Frequency PLL Division (PLLDIV2:PLLDIV0) 48 MHz 48 MHz 40 MHz 24 MHz 24 MHz 20 MHz 16 MHz 12 MHz 8 MHz 4 MHz Legend: Note 1: N/A ÷12 (000) ÷10 (001) ÷6 (010) N/A(1) ÷5 (011) ÷4 (100) ÷3 (101) ÷2 (110) ÷1 (111) Clock Mode (FOSC2:FOSC0) EC ECPLL ECPLL HSPLL, ECPLL EC, HS HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL MCU Clock Division (CPDIV1:CPDIV0) Microc
PIC18F87J50 FAMILY 2.4 Clock Sources and Oscillator Switching Like previous PIC18 enhanced devices, the PIC18F87J10 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F87J10 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.
PIC18F87J50 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 3.0 “Power-Managed Modes”. Note 1: The Timer1 oscillator must be enabled to select the Timer1 clock. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select the Timer1 clock source will be ignored.
PIC18F87J50 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER(1) R/W-0 R/W-1 R/W-1 R/W-0 R-1(2) U-1 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS — SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal
PIC18F87J50 FAMILY 2.5 Reference Clock Output OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on RE3 when the device is in Sleep mode. In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F87J10 family can also be configured to provide a reference clock output signal to a port pin.
PIC18F87J50 FAMILY 2.6 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. Unless the USB module is enabled, the OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F87J50 FAMILY 3.0 POWER-MANAGED MODES 3.1.1 The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: The PIC18F87J10 family devices provide the ability to manage power consumption by simply managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power.
PIC18F87J50 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON<3>) and T1RUN (T1CON<6>). In general, only one of these bits will be set while in a given power-managed mode.
PIC18F87J50 FAMILY Note: On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
PIC18F87J50 FAMILY 3.2.3 RC_RUN MODE On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC block while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18F87J50 FAMILY 3.3 Sleep Mode 3.4 The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-5). All clock source status bits are cleared. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate.
PIC18F87J50 FAMILY 3.4.1 PRI_IDLE MODE 3.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F87J50 FAMILY 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP.
PIC18F87J50 FAMILY NOTES: DS39775C-page 54 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 4.0 RESET The PIC18F87J10 family of devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) i) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Configuration Mismatch (CM) Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers.
PIC18F87J50 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — CM RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0
PIC18F87J50 FAMILY 4.2 Master Clear (MCLR) FIGURE 4-2: The MCLR pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. 4.3 D C POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs; it does not change for any other Reset event.
PIC18F87J50 FAMILY A CM Reset behaves similarly to a Master Clear Reset, RESET instruction, WDT time-out or Stack Event Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. 4.6 Power-up Timer (PWRT) PIC18F87J10 family devices incorporate an on-chip Power-up Timer (PWRT) to help regulate the Power-on Reset process. The PWRT is always enabled.
PIC18F87J50 FAMILY FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD 0V 1V MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 4.7 Reset State of Registers different Reset situations, as indicated in Table 4-1. These bits are used in software to determine the nature of the Reset. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 4-2 describes the Reset states for all of the Special Function Registers.
PIC18F87J50 FAMILY TABLE 4-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt TOSU Feature1 PIC18F8XJ5X ---0 0000 ---0 0000 ---0 uuuu(1) TOSH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(1) TOSL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(1) STKPTR Feature1 PIC18F8XJ5X 00-0 0000 uu-0 0000 uu-u uuuu(1) PCLATU Feature1
PIC18F87J50 FAMILY TABLE 4-2: Register INDF2 INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Feature1 PIC18F8XJ5X Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt N/A N/A N/A POSTINC2 Feature1 PIC18F8XJ5X N/A N/A N/A POSTDEC2 Feature1 PIC18F8XJ5X N/A N/A N/A PREINC2 Feature1 PIC18F8XJ5X N/A N/A N/A PLUSW2 Feature1 PIC18F8XJ5X N/A N/A N/A FSR2H Feature1 PIC18F8XJ5X ---
PIC18F87J50 FAMILY TABLE 4-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt ADRESH Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu ADRESL Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ADCON1 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu ANCON0 Fea
PIC18F87J50 FAMILY TABLE 4-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt IPR3 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu PIR3 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu(3) PIE3 Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu IPR2 Feature1 PIC18F8XJ5X 1111 1111 1111 1111 uuuu uuuu PIR2 Feature1
PIC18F87J50 FAMILY TABLE 4-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt PORTJ Feature1 PIC18F8XJ5X xxxx xxxx uuuu uuuu uuuu uuuu PORTH Feature1 PIC18F8XJ5X 0000 xxxx uuuu uuuu uuuu uuuu PORTG Feature1 PIC18F8XJ5X 000x xxxx 000u uuuu uuuu uuuu PORTF Feature1 PIC18F8XJ5X x00x x0-- u00u u0-- u00u u0-- PORTE Feature1
PIC18F87J50 FAMILY TABLE 4-2: Register PMADDRH INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT1H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMADDRL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT1L Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDIN
PIC18F87J50 FAMILY TABLE 4-2: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets Wake-up via WDT or Interrupt PMCONL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMMODEH Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMMODEL Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT2H Feature1 PIC18F8XJ5X 0000 0000 0000 0000 uuuu uuuu PMDOUT2
PIC18F87J50 FAMILY NOTES: DS39775C-page 68 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY MEMORY ORGANIZATION 5.1 There are two types of memory in PIC18 Flash microcontroller devices: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Additional detailed information on the operation of the Flash program memory is provided in Section 6.0 “Flash Program Memory”.
PIC18F87J50 FAMILY 5.1.1 HARD MEMORY VECTORS 5.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. Because PIC18F87J10 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information.
PIC18F87J50 FAMILY 5.1.3 PIC18F87J50 FAMILY PROGRAM MEMORY MODES The 80-pin devices in this family can address up to a total of 2 Mbytes of program memory. This is achieved through the External Memory Bus. There are two distinct operating modes available to the controllers: • Microcontroller (MC) • Extended Microcontroller (EMC) The program memory mode is determined by setting the EMB Configuration bits (CONFIG3L<5:4>), as shown in Register 5-1. (See also Section 25.
PIC18F87J50 FAMILY 5.1.4 EXTENDED MICROCONTROLLER MODE AND ADDRESS SHIFTING To avoid this, the Extended Microcontroller mode implements an address shifting option to enable automatic address translation. In this mode, addresses presented on the external bus are shifted down by the size of the on-chip program memory and are remapped to start at 0000h. This allows the complete use of the external memory device’s memory space.
PIC18F87J50 FAMILY 5.1.5 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F87J50 FAMILY 5.1.6.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value.
PIC18F87J50 FAMILY 5.1.6.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 1L. When STVREN is set, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset.
PIC18F87J50 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 5.2.2 An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F87J50 FAMILY 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.1.5 “Program Counter”).
PIC18F87J50 FAMILY 5.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F87J50 FAMILY FIGURE 5-7: DATA MEMORY MAP FOR PIC18F87J50 FAMILY DEVICES BSR<3:0> 00h = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When a = 0: Data Memory Map Bank 0 FFh 00h Access RAM GPR(1) (1) Bank 1 GPR 1FFh 200h FFh 00h GPR(1) Bank 2 FFh 00h Bank 3 2FFh 300h The first 96 bytes are general purpose RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15).
PIC18F87J50 FAMILY FIGURE 5-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 11 From Opcode(2) 11 11 11 11 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 5.3.3 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F87J50 FAMILY 5.3.5 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F40h to FFFh). A list of these registers is given inTable 5-3, Table 5-4 and Table 5-5. ALU’s STATUS register is described later in this section.
PIC18F87J50 FAMILY 5.3.5.1 Shared Address SFRs 5.3.5.2 In several locations in the SFR bank, a single address is used to access two different hardware registers. In these cases, a “legacy” register of the standard PIC18 SFR set (such as OSCCON, T1CON, etc.) shares its address with an alternate register. These alternate registers are associated with enhanced configuration options for peripherals, or with new device features not included in the standard PIC18 SFR map.
PIC18F87J50 FAMILY TABLE 5-5: File Name REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on Page: ---0 0000 61, 73 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 61, 73 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 61, 73 00-0 0000 61, 74 ---0 0000 61, 73 61, 73 TOSU STKPTR STKFUL STKUNF — PCLATU — — bit 21(1) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR SP4 SP3 SP2 SP1 SP0 Holding Register for
PIC18F87J50 FAMILY TABLE 5-5: File Name FSR2L REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx 62, 91 OV Z DC C ---x xxxx 62, 89 Indirect Data Memory Address Pointer 2 Low Byte STATUS — — — N Details on Page: Bit 3 TMR0H Timer0 Register High Byte 0000 0000 62, 193 TMR0L Timer0 Register Low Byte xxxx xxxx 62, 193 T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 62, 192 OSCCON(2)
PIC18F87J50 FAMILY TABLE 5-5: File Name ECCP1AS ECCP1DEL REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 P1RSEN P1DC6 P1DC5 P1DC4 Value on POR, BOR Details on Page: PSS1BD0 0000 0000 63, 232 P1DC0 0000 0000 63, 232 Bit 3 Bit 2 Bit 1 Bit 0 PSS1AC1 PSS1AC0 PSS1BD1 P1DC3 P1DC2 P1DC1 CCPR1H Capture/Compare/PWM Register 1 HIgh Byte xxxx xxxx 63, 232 CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 63, 232
PIC18F87J50 FAMILY TABLE 5-5: File Name REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: TRISJ(7) TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 64, 165 TRISH(7) TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 64, 163 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 64, 160 TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — —
PIC18F87J50 FAMILY TABLE 5-5: File Name REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: 65, 210 CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 65, 210 --00 0000 65, 210 CCP4CON — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 65, 210 CCPR5L Capture/Compare/PWM Regist
PIC18F87J50 FAMILY TABLE 5-5: File Name REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on Page: UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 66, 317 UEP3 —
PIC18F87J50 FAMILY 5.3.6 STATUS REGISTER The STATUS register, shown in Register 5-4, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18F87J50 FAMILY 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F87J50 FAMILY 5.4.3.1 FSR Registers and the INDF Operand mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target.
PIC18F87J50 FAMILY 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value.
PIC18F87J50 FAMILY 5.6 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands.
PIC18F87J50 FAMILY FIGURE 5-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 060h are not available in this addressing mode.
PIC18F87J50 FAMILY 5.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F87J50 FAMILY NOTES: DS39775C-page 96 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time or two bytes at a time.
PIC18F87J50 FAMILY FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 6.2 Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”.
PIC18F87J50 FAMILY REGISTER 6-1: EECON1: EEPROM CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0 — — WPROG FREE WRERR(1) WREN WR — bit 7 bit 0 Legend: S = Settable only bit (cannot be cleared in software) R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPROG: One Word-Wide Program bit 1 = Program 2 bytes on the next WR command 0
PIC18F87J50 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F87J50 FAMILY 6.3 Reading the Flash Program Memory TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 6-4: The internal program memory is typically organized by words.
PIC18F87J50 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR<21:10> point to the block being erased. TBLPTR<9:0> are ignored.
PIC18F87J50 FAMILY 6.5 Writing to Flash Program Memory The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. The programming block is 32 words or 64 bytes. Programming one word or two bytes at a time is also supported. Note 1: Unlike previous PIC® devices, members of the PIC18F87J10 family do not reset the holding registers after a write occurs.
PIC18F87J50 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base address ; of the memory block, minus 1 BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Row Erase operation ; disable interrupts MOVLW MOVWF MOVLW MOVWF MOVLW MOVW
PIC18F87J50 FAMILY 6.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). 3. The PIC18F87J10 family of devices have a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. 2. 4. 5. 6. 7. 8. Load the Table Pointer register with the address of the data to be written. (It must be an even address.
PIC18F87J50 FAMILY 6.5.3 6.6 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.4 Flash Program Operation During Code Protection See Section 25.6 “Program Verification and Code Protection” for details on code protection of Flash program memory.
PIC18F87J50 FAMILY 7.0 EXTERNAL MEMORY BUS Note: The External Memory Bus implemented on 64-pin devices. is not The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths of up to 20 bits. TABLE 7-1: The bus is implemented with 28 pins, multiplexed across four I/O ports.
PIC18F87J50 FAMILY 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions.
PIC18F87J50 FAMILY 7.2 Address and Data Width 7.2.1 The PIC18F87J10 family of devices can be independently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. The BW bit selects an 8-bit or 16-bit data bus width.
PIC18F87J50 FAMILY 7.3 Wait States While it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. In fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. To compensate for this, the External Memory Bus can be configured to add a fixed delay to each table operation using the bus. Wait states are enabled by setting the WAIT Configuration bit.
PIC18F87J50 FAMILY 7.6.1 16-BIT BYTE WRITE MODE During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus. The appropriate WRH or WRL control line is strobed on the LSb of the TBLPTR. Figure 7-1 shows an example of 16-Bit Byte Write mode for PIC18F87J10 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices.
PIC18F87J50 FAMILY 7.6.2 16-BIT WORD WRITE MODE Figure 7-2 shows an example of 16-Bit Word Write mode for PIC18F87J10 family devices. This mode is used for word-wide memories which include some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses.
PIC18F87J50 FAMILY 7.6.3 16-BIT BYTE SELECT MODE Figure 7-3 shows an example of 16-Bit Byte Select mode. This mode allows table write operations to word-wide external memories with byte selection capability. This generally includes both word-wide Flash and SRAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD15:AD0 bus. The WRH signal is strobed for each write cycle; the WRL pin is not used.
PIC18F87J50 FAMILY 7.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 and Figure 7-5.
PIC18F87J50 FAMILY 7.7 8-Bit Data Width Mode The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available on the external memory interface bus. The Output Enable signal (OE) will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The Least Significant bit of the address, BA0, must be connected to the memory devices in this mode.
PIC18F87J50 FAMILY 7.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-7 and Figure 7-8.
PIC18F87J50 FAMILY 7.8 Operation in Power-Managed Modes In alternate, power-managed Run modes, the external bus continues to operate normally. If a clock source with a lower speed is selected, bus operations will run at that speed. In these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory operations.
PIC18F87J50 FAMILY NOTES: DS39775C-page 118 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction EXAMPLE 8-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. ARG1, W ARG2 EXAMPLE 8-2: Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18F87J50 FAMILY Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F87J50 FAMILY 9.0 INTERRUPTS Members of the PIC18F87J10 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress.
PIC18F87J50 FAMILY FIGURE 9-1: PIC18F87J50 FAMILY INTERRUPT LOGIC Wake-up if in Idle or Sleep modes TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> Interrupt to CPU Vector to Location 0008h GIE/GIEH IPEN PIR3<7:0> PIE3<7:0> IPR3<7:0> IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2
PIC18F87J50 FAMILY 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F87J50 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Int
PIC18F87J50 FAMILY REGISTER 9-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low
PIC18F87J50 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F87J50 FAMILY REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in s
PIC18F87J50 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in softw
PIC18F87J50 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F87J50 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE USBIE BCL1IE LVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 CM1I
PIC18F87J50 FAMILY REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1
PIC18F87J50 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F87J50 FAMILY REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CM2IP CM1IP USBIP BCL1IP LVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CM2IP: Comparator 2 Interrupt Priority bit 1 = High priority 0
PIC18F87J50 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit
PIC18F87J50 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F87J50 FAMILY 9.6 INTx Pin Interrupts 9.7 TMR0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F87J50 FAMILY 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to nine ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
PIC18F87J50 FAMILY Table 10-2 summarizes the output capabilities of the ports. Refer to the “Absolute Maximum Ratings” in Section 28.0 “Electrical Characteristics” for more details. TABLE 10-2: Port OUTPUT DRIVE LEVELS Drive PORTA When the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5.5V (Figure 10-2). When a digital logic high signal is output, it is pulled up to the higher voltage level.
PIC18F87J50 FAMILY REGISTER 10-1: ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CCP5OD CCP4OD ECCP3OD ECCP2OD ECCP1OD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 CCP5OD:CCP4OD: CCPx Open-Drain Output Enable bits 1 = Open-drain output on CCPx pin (Capture/PWM modes) en
PIC18F87J50 FAMILY REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers 10.
PIC18F87J50 FAMILY TABLE 10-4: Pin Name RA0/AN0 PORTA FUNCTIONS Function TRIS Setting DIG LATA<0> data output; not affected by analog input. I TTL PORTA<0> data input; disabled when analog input enabled. I ANA A/D input channel 0. Default input configuration on POR; does not affect digital output. O DIG LATA<1> data output; not affected by analog input. I TTL PORTA<1> data input; disabled when analog input enabled. AN1 0 1 1 I ANA A/D input channel 1.
PIC18F87J50 FAMILY TABLE 10-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 6 PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 65 LATA — — LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 64 — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 64 PCFG7 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 TRISA (1) ANCON0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: Bit 7 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
PIC18F87J50 FAMILY 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. All pins on PORTB are digital only and tolerate voltages up to 5.5V. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output.
PIC18F87J50 FAMILY TABLE 10-6: PORTB FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RB0/FLT0/INT0 RB0 0 O DIG LATB<0> data output. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. RB1/INT1/ PMA4 RB2/INT2/ PMA3 RB3/INT3/ ECCP2/P2A/ PMA2 RB4/KBI0/ PMA1 FLT0 1 I ST Enhanced PWM Fault input (ECCP1 module); enabled in software. INT0 1 I ST External interrupt 0 input. RB1 0 O DIG LATB<1> data output.
PIC18F87J50 FAMILY TABLE 10-7: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 65 LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 64 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 64 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 61 INT2IF INT1IF 61 INTCON GIE/GIEH PEIE/GIEL INTCON2
PIC18F87J50 FAMILY 10.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. Only PORTC pins, RC2 through RC7, are digital only pins and can tolerate input voltages up to 5.5V. PORTC is multiplexed with CCP, MSSP and EUSART peripheral functions (Table 10-8). The pins have Schmitt Trigger input buffers. The pins for CCP, SPI and EUSART are also configurable for open-drain output whenever these functions are active.
PIC18F87J50 FAMILY TABLE 10-8: Pin Name RC0/T1OSO/ T13CKI RC1/T1OSI/ ECCP2/P2A RC2/ECCP1/ P1A RC3/SCK1/ SCL1 PORTC FUNCTIONS Function TRIS Setting I/O I/O Type RC0 0 O DIG LATC<0> data output. 1 I ST PORTC<0> data input. T1OSO x O ANA T13CKI 1 I ST Timer1/Timer3 counter input. RC1 0 O DIG LATC<1> data output. 1 I ST T1OSI x I ANA Timer1 oscillator input; enabled when Timer1 oscillator enabled. Disables digital I/O.
PIC18F87J50 FAMILY TABLE 10-8: PORTC FUNCTIONS (CONTINUED) Pin Name Function TRIS Setting I/O I/O Type RC7/RX1/DT1 RC7 0 O DIG 1 I ST PORTC<7> data input. RX1 1 I ST Asynchronous serial receive data input (EUSART1 module). DT1 1 O DIG Synchronous serial data output (EUSART1 module); takes priority over port data. 1 I ST Synchronous serial data input (EUSART1 module). User must configure as an input. Legend: Note 1: PORTC LATC<7> data output.
PIC18F87J50 FAMILY 10.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. All pins on PORTD are digital only and tolerate voltages up to 5.5V. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset. On 80-pin devices, PORTD is multiplexed with the system bus as part of the external memory interface.
PIC18F87J50 FAMILY TABLE 10-10: PORTD FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RD0 0 O DIG LATD<0> data output. 1 I ST PORTD<0> data input. AD0(2) x O DIG External memory interface, address/data bit 0 output.(1) x I TTL External memory interface, data bit 0 input.(1) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input. 0 O DIG LATD<1> data output.
PIC18F87J50 FAMILY TABLE 10-10: PORTD FUNCTIONS (CONTINUED) Pin Name RD6/AD6/ PMD6/SCK2/ SCL2 Function TRIS Setting I/O I/O Type RD6 0 O DIG AD6(2) PMD6(3) SCK2 SCL2 RD7/AD7/ PMD7/SS2 RD7 AD7(2) PMD7(3) SS2 Legend: Note 1: 2: 3: Description LATD<6> data output. 1 I ST x O DIG-3 PORTD<6> data input. x I TTL External memory interface, data bit 6 input.(1) x O DIG Parallel Master Port data out. x I TTL Parallel Master Port data input.
PIC18F87J50 FAMILY 10.6 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. All pins on PORTE are digital only and tolerate voltages up to 5.5V. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset. On 80-pin devices, PORTE is multiplexed with the system bus as part of the external memory interface.
PIC18F87J50 FAMILY TABLE 10-12: Pin Name RE0/AD8/ PMRD/P2D PORTE FUNCTIONS Function TRIS Setting I/O I/O Type RE0 0 O DIG LATE<0> data output. 1 I ST PORTE<0> data input. x O DIG External memory interface, address/data bit 8 output.(2) x I TTL External memory interface, data bit 8 input.(2) x O DIG Parallel Master Port read strobe pin. x I TTL Parallel Master Port read pin. P2D 0 O DIG ECCP2 Enhanced PWM output, channel D; takes priority over port and PMP data.
PIC18F87J50 FAMILY TABLE 10-12: Pin Name PORTE FUNCTIONS (CONTINUED) Function TRIS Setting I/O I/O Type RE5 0 O DIG LATE<5> data output. RE5/AD13/ PMA11/P1C 1 I ST PORTE<5> data input. x O DIG External memory interface, address/data bit 13 output.(2) x I TTL External memory interface, data bit 13 input.(2) PMA11 x O DIG Parallel Master Port address. (1) 0 O DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP data.
PIC18F87J50 FAMILY 10.7 PORTF, LATF and TRISF Registers PORTF is a 6-bit wide, bidirectional port. RF2, RF5 and RF6 are analog inputs. These ports are configured as analog inputs on a device Reset. All pins on PORTF are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Pins, RF3 and RF4, are multiplexed with the USB module. Depending on the configuration of the module, they can serve as the differential data lines for the on-chip USB transceiver.
PIC18F87J50 FAMILY TABLE 10-14: PORTF FUNCTIONS Pin Name Function TRIS Setting I/O I/O Type RF2 0 O DIG LATF<2> data output; not affected by analog input. 1 I ST PORTF<2> data input; disabled when analog input enabled. PMA5 x O DIG Parallel Master Port address. AN7 1 I ANA A/D input channel 7. Default configuration on POR. C2INB x I ANA Comparator 2 input B. RF3 1 I ST PORTF<3> data input; disabled when analog input enabled.
PIC18F87J50 FAMILY TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name PORTF LATF TRISF ANCON0 (1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RF7 RF6 RF5 RF4 RF3 RF2 — — 65 — 64 64 LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 — TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 — — PCFG7 ANCON1(1) PCFG15 — — PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 63 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 — — 63 Legend: — = unimplemented, read as ‘0’.
PIC18F87J50 FAMILY 10.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corresponding Data Direction register is TRISG. All pins on PORTG are digital only and tolerate voltages up to 5.5V. PORTG is multiplexed with EUSART2 functions (Table 10-16). PORTG pins have Schmitt Trigger input buffers. PORTG has pins multiplexed with the Parallel Master Port. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTG pin.
PIC18F87J50 FAMILY TABLE 10-16: PORTG FUNCTIONS Pin Name RG0/PMA8/ ECCP3/P3A Function TRIS Setting I/O I/O Type RG0 0 O DIG 1 I ST PORTG<0> data input. x O DIG Parallel Master Port address. O DIG ECCP3 compare and PWM output; takes priority over port data. PMA8 ECCP3 RG1/PMA7/ TX2/CK2/ RG2/PMA6/ RX2/DT2 I ST ECCP3 capture input. 0 O DIG ECCP3 Enhanced PWM output, channel A; takes priority over port and PMP data.
PIC18F87J50 FAMILY TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 3 Bit 2 Reset Values on Page: RG1 RG0 65 LATG1 LATG0 64 TRISG0 64 Bit 6 Bit 5 RDPU REPU RJPU(1) RG4 RG3 RG2 LATG — — — LATG4 LATG3 LATG2 TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 PORTG Bit 4 Bit 0 Bit 7 Bit 1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’.
PIC18F87J50 FAMILY 10.9 Note: PORTH, LATH and TRISH Registers PORTH is available only on 80-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. PORTH pins <3:0> are digital only and tolerate voltages up to 5.5V. All pins on PORTH are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. When the external memory interface is enabled, four of the PORTH pins function as the high-order address lines for the interface.
PIC18F87J50 FAMILY TABLE 10-18: PORTH FUNCTIONS Pin Name RH0/A16 RH1/A17 RH2/A18/ PMD7 RH3/A19/ PMD6 Function TRIS Setting I/O I/O Type RH0 0 O DIG LATH<0> data output. 1 I ST PORTH<0> data input. A16 x O DIG External memory interface, address line 16. Takes priority over port data. RH1 0 O DIG LATH<1> data output. 1 I ST PORTH<1> data input. A17 x O DIG External memory interface, address line 17. Takes priority over port data. RH2 0 O DIG LATH<2> data output.
PIC18F87J50 FAMILY TABLE 10-18: PORTH FUNCTIONS (CONTINUED) Pin Name RH7/PMWR/ AN15/P1B/ Function TRIS Setting I/O I/O Type RH7 0 O DIG 1 I ST PORTH<7> data input. PMWR(2) x O DIG Parallel Master Port write strobe. x I TTL Parallel Master Port write in. I ANA A/D input channel 15. Default input configuration on POR; does not affect digital output. O DIG ECCP1 Enhanced PWM output, channel B; takes priority over port and PMP data.
PIC18F87J50 FAMILY 10.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. All pins on PORTJ are digital only and tolerate voltages up to 5.5V. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset.
PIC18F87J50 FAMILY TABLE 10-20: PORTJ FUNCTIONS Pin Name RJ0/ALE RJ1/OE RJ2/WRL RJ3/WRH RJ4/BA0 RJ5/CE RJ6/LB RJ7/UB Function TRIS Setting I/O I/O Type RJ0 0 O DIG LATJ<0> data output. 1 I ST PORTJ<0> data input. ALE x O DIG External memory interface address latch enable control output; takes priority over digital I/O. RJ1 0 O DIG LATJ<1> data output. 1 I ST PORTJ<1> data input.
PIC18F87J50 FAMILY NOTES: DS39775C-page 166 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 11.0 PARALLEL MASTER PORT The Parallel Master Port module (PMP) is a parallel, 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. The PMP module can be configured to serve as either a Parallel Master Port or as a Parallel Slave Port.
PIC18F87J50 FAMILY 11.1 Module Registers The PMCON registers (Register 11-1 and Register 11-2) control basic module operations, including turning the module on or off. They also configure address multiplexing and control strobe configuration. The PMP module has a total of 14 Special Function Registers for its operation, plus one additional register to set configuration options. Of these, 8 registers are used for control and 6 are used for PMP data transfer. 11.1.
PIC18F87J50 FAMILY REGISTER 11-2: PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 and PMCS2 function as chip select 01 = PMCS2 functions as chip select, PM
PIC18F87J50 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 6-5 IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt g
PIC18F87J50 FAMILY REGISTER 11-4: R/W-0 WAITB1 PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE R/W-0 (1) R/W-0 (1) WAITB0 WAITM3 R/W-0 WAITM2 R/W-0 WAITM1 R/W-0 WAITM0 R/W-0 WAITE1 (1) R/W-0 WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address
PIC18F87J50 FAMILY REGISTER 11-6: PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 PTEN7:PTEN2: PMP Address Port Enable bits 1 = PMA<7:2> function as PMP address lines 0 = PMA<7:2> function as port I/O bit 1-0 PTEN1:PT
PIC18F87J50 FAMILY REGISTER 11-8: PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE R-1 R/W-0 U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF:
PIC18F87J50 FAMILY 11.1.2 DATA REGISTERS The PMP module uses 6 registers for transferring data into and out of the microcontroller. They are arranged as three pairs to allow the option of 16-bit data operations: • • • • PMDIN1H and PMDIN1L PMDIN2H and PMDIN2L PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L PMDOUT2H and PMDOUT2L The PMDIN1 register is used for incoming data in Slave modes, and both input and output data in Master modes. The PMDIN2 register is used for buffering input data in select Slave modes.
PIC18F87J50 FAMILY 11.1.4 PMP MULTIPLEXING OPTIONS(80-PINS DEVICES) By default, the PMP and the External Memory Bus (EMB) multiplex some of their signals to the same I/O pins on PORTD and PORTE. It is possible that some applications may require the use of both modules at the same time. For these instances, the 80-pin devices can be configured to multiplex the PMP to different I/O ports.
PIC18F87J50 FAMILY 11.2.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the lower PMDIN1L register. The PMPIF and IBF flag bits are set when the write ends.The timing for the control signals in Write mode is shown in Figure 11-3. The polarity of the control signals are configurable. FIGURE 11-3: 11.2.
PIC18F87J50 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE PORT MODE Buffered Parallel Slave Port mode is functionally identical to the legacy Parallel Slave Port mode with one exception: the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM<1:0> bits are set to ‘11’, the PMP module will act as the buffered Parallel Slave Port.
PIC18F87J50 FAMILY 11.2.5 ADDRESSABLE PARALLEL SLAVE PORT MODE In the Addressable Parallel Slave Port mode (PMMODEH<1:0> = 01), the module is configured with two extra inputs, PMA<1:0>, which are the address lines 1 and 0. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. As with legacy Buffered mode, data is output from PMDOUT1L, PMDOUT1H, PMDOUT2L and PMDOUT2H, and is read in PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H.
PIC18F87J50 FAMILY 11.2.5.1 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from one of the four output bytes is presented onto PMD<7:0>. Which byte is read depends on the 2-bit address placed on ADDR[1:0]. Table 11-2 shows the corresponding FIGURE 11-7: output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. The OBxE flag bit is set when all the buffers are empty.
PIC18F87J50 FAMILY 11.3 MASTER PORT MODES In its Master modes, the PMP module provides an 8-bit data bus, up to 16 bits of address, and all the necessary control signals to operate a variety of external parallel devices, such as memory devices, peripherals and slave microcontrollers. To use the PMP as a master, the module must be enabled (PMPEN = 1) and the mode must be set to one of the two possible Master modes (PMMODEH<1:0> = 10 or 11).
PIC18F87J50 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F PMA<13:0> PMD<7:0> PMCS1 PMCS2 Address Bus FIGURE 11-10: PMRD Data Bus PMWR Control Lines PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 PMCS2 PMALL PMRD PMWR FIGURE 11-11: Address Bus Multiplexed Data and Address Bus Control Lines FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE ST
PIC18F87J50 FAMILY 11.3.5 CHIP SELECT FEATURES Up to two chip select lines, PMCS1 and PMCS2, are available for the Master modes of the PMP. The two chip select lines are multiplexed with the Most Significant bits of the address bus (PMADDRH<6> and PMADDRH<7>). When a pin is configured as a chip select, it is not included in any address auto-increment/ decrement. The function of the chip select signals is configured using the chip select function bits (PMCONL<7:6>). 11.3.
PIC18F87J50 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address, as well as wait states.
PIC18F87J50 FAMILY FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 Address<7:0> PMD<7:0> Data PMA<13:8> PMWR PMRD PMALL PMPIF BUSY FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS2 PMCS1 Address<7:0> PMD<7:0> Data PMA<13:8> PMWR PMRD PM
PIC18F87J50 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 Address<7:0> PMD<7:0> Data PMA<13:8> PMRD/PMWR PMENB PMALL PMPIF BUSY FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 Address<7:0> PMD<7:0> Address<15:8> Data PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-2
PIC18F87J50 FAMILY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 LSB PMD<7:0> MSB PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 PMD<7:0> LSB MSB PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS
PIC18F87J50 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 Address<7:0> PMD<7:0> LSB MSB PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS2 PMCS1 Address<7:0> PMD<7:0> Address<15:8> LSB MSB PMWR PMRD PMBE
PIC18F87J50 FAMILY 11.4 Application Examples 11.4.1 This section introduces some potential applications for the PMP module. FIGURE 11-27: Figure 11-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address.
PIC18F87J50 FAMILY 11.4.3 PARALLEL EEPROM EXAMPLE Figure 11-30 shows an example connecting parallel EEPROM to the PMP. Figure 11-31 shows a slight variation to this, configuring the connection for 16-bit data from a single EEPROM.
PIC18F87J50 FAMILY TABLE 11-3: Name INTCON REGISTERS ASSOCIATED WITH PMP MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PMCONH PMPEN — PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 66 CSF1 CSF
PIC18F87J50 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow REGISTER 12-1: The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection.
PIC18F87J50 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
PIC18F87J50 FAMILY 12.3 Prescaler 12.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS2:T0PS0 bits (T0CON<3:0>) which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable.
PIC18F87J50 FAMILY NOTES: DS39775C-page 194 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 13.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt on overflow • Reset on CCP Special Event Trigger • Device clock status flag (T1RUN) REGISTER 13-1: A simplified block diagram of the Timer1 module is shown in Figure 13-1.
PIC18F87J50 FAMILY 13.1 Timer1 Operation cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter When Timer1 is enabled, the RC1/T1OSI and RC0/T1OSO/T13CKI pins become inputs. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F87J50 FAMILY 13.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit, T1CON<7>, is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register.
PIC18F87J50 FAMILY If a high-speed circuit must be located near the oscillator (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 13-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. FIGURE 13-4: OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. 13.
PIC18F87J50 FAMILY The Real-Time Clock application code in Example 13-1 shows a typical ISR for Timer1, as well as the optional code required if the update cannot be done reliably within the required interval. EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1CON secs mins .
PIC18F87J50 FAMILY TABLE 13-2: Name INTCON REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 IPR1 GIE/GIEH PEIE/GIEL Bit 5 TMR1L(1) Timer1 Register Low Byte TMR1H(1) Timer1 Register
PIC18F87J50 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation • 8-Bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional use as the shift clock for the MSSP modules In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4).
PIC18F87J50 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1<1>).
PIC18F87J50 FAMILY 15.0 TIMER3 MODULE The Timer3 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger REGISTER 15-1: A simplified block diagram of the Timer3 module is shown in Figure 15-1.
PIC18F87J50 FAMILY 15.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18F87J50 FAMILY 15.2 Timer3 16-Bit Read/Write Mode 15.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 15-2). When the RD16 control bit (T3CON<7>) is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18F87J50 FAMILY NOTES: DS39775C-page 206 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 16.0 TIMER4 MODULE 16.1 The Timer4 timer module has the following features: • • • • • • 8-bit timer register (TMR4) 8-bit period register (PR4) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR4 match of PR4 Timer4 has a control register shown in Register 16-1. Timer4 can be shut off by clearing control bit, TMR4ON (T4CON<2>), to minimize power consumption.
PIC18F87J50 FAMILY 16.2 Timer4 Interrupt 16.3 The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: Output of TMR4 The output of TMR4 (before the postscaler) is used only as a PWM time base for the ECCP/CCP modules. It is not used as a baud rate clock for the MSSP modules as is the Timer2 output.
PIC18F87J50 FAMILY 17.0 CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F87J10 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ECCP3) implement standard Capture and Compare modes, as well as Enhanced PWM modes. These are discussed in Section 18.0 “Enhanced Capture/Compare/PWM (ECCP) Module”.
PIC18F87J50 FAMILY 17.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 17.1.1 17.1.2 CCP MODULES AND TIMER RESOURCES The ECCP/CCP modules utilize Timers 1, 2, 3 or 4, depending on the mode selected.
PIC18F87J50 FAMILY 17.2 Capture Mode 17.2.3 When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCPx pin.
PIC18F87J50 FAMILY 17.3 Compare Mode Note: In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • • • • driven high driven low toggled (high-to-low or low-to-high) remains unchanged (that is, reflects the state of the I/O latch) 17.3.2 17.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCPxM3:CCPxM0 = 1010), the corresponding CCPx pin is not affected.
PIC18F87J50 FAMILY TABLE 17-2: Name INTCON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 61 IPEN — CM RI TO PD POR BOR 62 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 RCON PIR2 OS
PIC18F87J50 FAMILY 17.4 PWM Mode 17.4.1 In Pulse-Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. Note: Clearing the CCP4CON or CCP5CON register will force the RG3 or RG4 output latch (depending on device configuration) to the default low level. This is not the PORTG I/O data latch.
PIC18F87J50 FAMILY The CCPRxH register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPRxH and 2-bit latch match TMR2 (TMR4), concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 (TMR4) prescaler, the CCPx pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by Equation 17-3: 17.4.
PIC18F87J50 FAMILY TABLE 17-4: Name INTCON REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 IPEN — CM RI TO PD POR BOR 62 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 RCON PIR3 SSP2IF BCL2IF
PIC18F87J50 FAMILY 18.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The control register for the Enhanced CCP module is shown in Register 18-1. It differs from the CCP4CON/ CCP5CON registers in that the two Most Significant bits are implemented to control PWM functionality. In the PIC18F87J10 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities.
PIC18F87J50 FAMILY 18.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration.
PIC18F87J50 FAMILY TABLE 18-1: PIN CONFIGURATIONS FOR ECCP1 CCP1CON Configuration ECCP Mode RC2 RE6 RE5 RG4 RH7 RH6 All Feature1 Devices: Compatible CCP 00xx 11xx ECCP1 RE6 RE5 RG4/CCP5 N/A N/A Dual PWM 10xx 11xx P1A P1B RE5 RG4/CCP5 N/A N/A x1xx 11xx P1A P1B P1C P1D N/A N/A Quad PWM(1) PIC18F8XJ5X Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP1 RE6/AD14 RE5/AD13 RG4/CCP5 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P1A RE6/AD14 RE5/AD13 RG4/C
PIC18F87J50 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON Configuration ECCP Mode RG0 RE4 RE3 RG3 RH5 RH4 Feature1 Devices: Compatible CCP 00xx 11xx ECCP3 RE4 RE3 RG3/CCP4 N/A N/A Dual PWM 10xx 11xx P3A P3B RE3 RG3/CCP4 N/A N/A x1xx 11xx P3A P3B P3C P3D N/A N/A Quad PWM(1) PIC18F8XJ5X Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP 00xx 11xx ECCP3 RE6/AD14 RE5/AD13 RG3/CCP4 RH7/AN15 RH6/AN14 Dual PWM 10xx 11xx P3A RE6/AD14 RE5/AD13 RG3/CCP4
PIC18F87J50 FAMILY 18.4 Enhanced PWM Mode The Enhanced PWM mode provides additional PWM output options for a broader range of control applications. The module is a backward compatible version of the standard CCP module and offers up to four outputs, designated PxA through PxD. Users are also able to select the polarity of the signal (either active-high or active-low).
PIC18F87J50 FAMILY 18.4.2 PWM DUTY CYCLE Note: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation: 18.4.
PIC18F87J50 FAMILY FIGURE 18-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) CCP1CON<7:6> SIGNAL 0 PR2 + 1 Duty Cycle Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated (Half-Bridge) 10 P1B Modulated P1A Active (Full-Bridge, Forward) 01 P1B Inactive P1C Inactive P1D Modulated P1A Inactive (Full-Bridge, Reverse) 11 P1B Modulated P1C Active P1D Inactive FIGURE 18-3: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) CCP1CON<7:6> SIGNAL 0 Duty Cycle PR2 + 1 Period 00 (
PIC18F87J50 FAMILY 18.4.4 HALF-BRIDGE MODE FIGURE 18-4: In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complementary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge applications, as shown in Figure 18-5, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18F87J50 FAMILY 18.4.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin P1A is continuously active and pin P1D is modulated. In the Reverse mode, pin P1C is continuously active and pin P1B is modulated. These are illustrated in Figure 18-6. FIGURE 18-6: P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table 18-1, Table 18-2 and Table 18-3.
PIC18F87J50 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE OUTPUT APPLICATION V+ PIC18F87J50 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 18.4.5.1 Direction Change in Full-Bridge Output Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F87J50 FAMILY FIGURE 18-8: PWM DIRECTION CHANGE Period(1) SIGNAL Period P1A (Active-High) P1B (Active-High) DC P1C (Active-High) (Note 2) P1D (Active-High) DC Note 1: The direction bit in the ECCP1 Control register (CCP1CON<7>) is written at any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of 4 TOSC, 16 TOSC or 64 TOSC, depending on the Timer2 prescaler value.
PIC18F87J50 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F87J50 FAMILY REGISTER 18-3: ECCPxAS: ECCPx AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPxASE ECCPxAS2 ECCPxAS1 ECCPxAS0 PSSxAC1 PSSxAC0 PSSxBD1 PSSxBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPxASE: ECCPx Auto-Shutdown Event Status bit 0 = ECCPx outputs are operating 1 = A shutdown event has occurred; ECCP
PIC18F87J50 FAMILY The CCP1M1:CCP1M0 bits (CCP1CON<1:0>) allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pins are configured as outputs. Changing the polarity configuration while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits.
PIC18F87J50 FAMILY 18.4.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCPx module for PWM operation: 1. 2. 3. 4. 5. 6. 7. Configure the PWM pins PxA and PxB (and PxC and PxD, if used) as inputs by setting the corresponding TRIS bits. Set the PWM period by loading the PR2 (PR4) register.
PIC18F87J50 FAMILY TABLE 18-5: Name INTCON RCON REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Reset Values on Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 IPEN — CM RI TO PD POR BOR 62 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR2 OSC
PIC18F87J50 FAMILY 19.0 19.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc.
PIC18F87J50 FAMILY 19.3.1 REGISTERS SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. Each MSSP module has four registers for SPI mode operation. These are: In receive operations, SSPxSR and SSPxBUF together create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.
PIC18F87J50 FAMILY REGISTER 19-2: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 WCOL SSPOV(1) R/W-0 (2) SSPEN R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (mu
PIC18F87J50 FAMILY 19.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
PIC18F87J50 FAMILY 19.3.4 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPxCON registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins.
PIC18F87J50 FAMILY 19.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 1, Figure 19-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18F87J50 FAMILY 19.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC18F87J50 FAMILY FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPxSR to SSPxBUF FIGURE 19-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 7 bi
PIC18F87J50 FAMILY 19.3.9 OPERATION IN POWER-MANAGED MODES In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 2.4 “Clock Sources and Oscillator Switching” for additional information. 19.3.
PIC18F87J50 FAMILY TABLE 19-2: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 64 PIE
PIC18F87J50 FAMILY 19.4 I2C Mode 19.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support), and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC18F87J50 FAMILY REGISTER 19-3: R/W-0 SSPxSTAT: MSSPx STATUS REGISTER (I2C™ MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2,3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled fo
PIC18F87J50 FAMILY REGISTER 19-4: R/W-0 WCOL SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C™ MODE) R/W-0 R/W-0 SSPOV SSPEN(1) R/W-0 CKP R/W-0 SSPM3 (2) R/W-0 SSPM2 (2) R/W-0 SSPM1 (2) R/W-0 SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C cond
PIC18F87J50 FAMILY REGISTER 19-5: R/W-0 GCEN SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ MASTER MODE) R/W-0 ACKSTAT R/W-0 ACKDT (1) R/W-0 (2) ACKEN R/W-0 (2) RCEN R/W-0 PEN (2) R/W-0 (2) RSEN R/W-0 SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received
PIC18F87J50 FAMILY REGISTER 19-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enables interrupt when a general call address (0000h) is received in the SS
PIC18F87J50 FAMILY 19.4.2 OPERATION The MSSP module functions are enabled by setting the MSSP Enable bit, SSPEN (SSPxCON1<5>). The SSPxCON1 register allows control of the I2C operation.
PIC18F87J50 FAMILY 19.4.3.2 Address Masking Modes Masking an address bit causes that bit to become a “don't care”. When one address bit is masked, two addresses will be Acknowledged and cause an interrupt. It is possible to mask more than one address bit at a time, which greatly expands the number of addresses Acknowledged. 2 The I C Slave behaves the same way whether address masking is used or not.
PIC18F87J50 FAMILY 19.4.3.4 7-Bit Address Masking Mode Unlike 5-Bit Address Masking mode, 7-Bit Address Masking mode uses a mask of up to 8 bits (in 10-bit addressing) to define a range of addresses than can be Acknowledged, using the lowest bits of the incoming address. This allows the module to Acknowledge up to 127 different addresses with 7-bit addressing, or 255 with 10-bit addressing (see Example 19-3).
PIC18F87J50 FAMILY 19.4.3.5 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and the SDAx line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit, BF (SSPxSTAT<0>), is set or bit, SSPOV (SSPxCON1<6>), is set.
DS39775C-page 252 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPxCON1<4>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPxBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPxBUF is still full.
© 2009 Microchip Technology Inc. 2 A6 Note 3 A5 4 X 5 A3 6 X 1 3 4 D4 Cleared in software SSPxBUF is read 2 D5 5 D3 6 D2 7 D1 8 D0 In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt. 9 D6 x = Don’t care (i.e., address bit can either be a ‘1’ or a ‘0’).
DS39775C-page 254 2 Data in sampled 1 A6 CKP (SSPxCON1<4>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 R/W = 0 9 ACK 3 D5 4 5 D3 SSPxBUF is written in software 6 D2 Transmitting Data D4 Cleared in software 2 D6 CKP is set in software SCLx held low while CPU responds to SSPxIF 1 D7 7 8 D0 9 From SSPxIF ISR D1 ACK 1 D7 4 D4 5 D3 Cleared in software 3 D5 6 D2 CKP is set in software SSPxBUF is written
© 2009 Microchip Technology Inc. 2 1 3 1 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 2 X 4 5 A3 6 A2 4 5 6 Cleared in software 3 7 8 9 1 2 4 5 6 Cleared in software 3 D3 D2 Receive Data Byte D1 D0 ACK D7 D6 D5 D4 Cleared by hardware when SSPxADD is updated with high byte of address 2 D3 D2 Note that the Most Significant bits of the address are not affected by the bit masking.
DS39775C-page 256 2 1 3 1 4 1 5 0 7 A8 8 UA is set indicating that the SSPxADD needs to be updated SSPxBUF is written with contents of SSPxSR 6 A9 9 (CKP does not reset to ‘0’ when SEN = 0) CKP (SSPxCON1<4>) UA (SSPxSTAT<1>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) Cleared in software SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPxADD needs to be updated Cleared by hardware when SSPxADD is updated with low
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 19.4.4 CLOCK STRETCHING Both 7-Bit and 10-Bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPxCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCLx pin to be held low at the end of each data receive sequence. 19.4.4.
PIC18F87J50 FAMILY 19.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sampled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has FIGURE 19-14: already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx.
DS39775C-page 260 2 A6 CKP (SSPxCON1<4>) SSPOV (SSPxCON1<6>) BF (SSPxSTAT<0>) SSPxIF (PIR1<3> or PIR3<7>) 1 SCLx S A7 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPxBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 19.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPxSR is transferred to the SSPxBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPxIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F87J50 FAMILY MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPxCON1 and by setting the SSPEN bit. In Master mode, the SCLx and SDAx lines are manipulated by the MSSP hardware if the TRIS bits are set. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F87J50 FAMILY 19.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDAx while SCLx outputs the serial clock.
PIC18F87J50 FAMILY 19.4.7 BAUD RATE 19.4.7.1 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPxADD register (Figure 19-19). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC18F87J50 FAMILY 19.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the FIGURE 19-20: SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and begins counting.
PIC18F87J50 FAMILY 19.4.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN (SSPxCON2<0>). If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<6:0> and starts its count. If SCLx and SDAx are both sampled high when the Baud Rate Generator times out (TBRG), the SDAx pin is driven low.
PIC18F87J50 FAMILY 19.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit (SSPxCON2<1>) is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCLx pin is asserted low. When the SCLx pin is sampled low, the Baud Rate Generator is loaded with the contents of SSPxADD<5:0> and begins counting.
PIC18F87J50 FAMILY 19.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted (see data hold time specification parameter 106).
DS39775C-page 270 S R/W PEN SEN BF (SSPxSTAT<0>) SSPxIF SCLx SDAx A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPxBUF written 1 9 D7 1 SCLx held low while CPU responds to SSPxIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W, start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written in software Cleared in software service routine from MSSP interrupt 2 D6 Trans
© 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 19.4.12 ACKNOWLEDGE SEQUENCE TIMING 19.4.13 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPxCON2<2>). At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC18F87J50 FAMILY 19.4.14 SLEEP OPERATION 19.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 19.4.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 19.4.
PIC18F87J50 FAMILY 19.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx is sampled low at the beginning of the Start condition (Figure 19-28). SCLx is sampled low before SDAx is asserted low (Figure 19-29). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 19-30).
PIC18F87J50 FAMILY FIGURE 19-29: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC18F87J50 FAMILY 19.4.17.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 19-31). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC18F87J50 FAMILY 19.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD<6:0> and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 19-33).
PIC18F87J50 FAMILY TABLE 19-4: Name REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE
PIC18F87J50 FAMILY 20.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of two serial I/O modules. (Generically, the EUSART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F87J50 FAMILY REGISTER 20-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F87J50 FAMILY REGISTER 20-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) b
PIC18F87J50 FAMILY REGISTER 20-3: BAUDCONx: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurre
PIC18F87J50 FAMILY 20.1 Baud Rate Generator (BRG) The BRG is a dedicated, 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>) selects 16-bit mode. The SPBRGHx:SPBRGx register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTAx<2>) and BRG16 (BAUDCONx<3>) also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F87J50 FAMILY EXAMPLE 20-1: CALCULATING BAUD RATE ERROR For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGHx:SPBRGx] + 1)) Solving for SPBRGHx:SPBRGx: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F87J50 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz Actual Rate (K) FOSC = 10.000 MHz Actual Rate (K) FOSC = 8.000 MHz Actual Rate (K) Actual Rate (K) % Error 0.3 — — — — — — — — — — — — 1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103 2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.
PIC18F87J50 FAMILY TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) SPBRG value % Error FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1.2 1.200 0.02 2082 1.200 -0.
PIC18F87J50 FAMILY 20.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F87J50 FAMILY FIGURE 20-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RXx pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCxIF bit (Interrupt) Read RCREGx SPBRGx XXXXh 1Ch SPBRGHx XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F87J50 FAMILY 20.2 EUSART Asynchronous Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx register is empty and the TXxIF flag bit is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF will be set regardless of the state of TXxIE; it cannot be cleared in software.
PIC18F87J50 FAMILY FIGURE 20-4: ASYNCHRONOUS TRANSMISSION Write to TXREGx Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 20-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx Word 2 Word 1 BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 1 TCY TXxIF bit (Interrupt Reg.
PIC18F87J50 FAMILY 20.2.2 EUSART ASYNCHRONOUS RECEIVER 20.2.3 The receiver block diagram is shown in Figure 20-6. The data is received on the RXx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F87J50 FAMILY FIGURE 20-7: ASYNCHRONOUS RECEPTION Start bit RXx (pin) bit 0 bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx Read Rcv Buffer Reg RCREGx bit 7/8 RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F87J50 FAMILY 20.2.4.1 Special Considerations Using Auto-Wake-up 20.2.4.2 Since auto-wake-up functions by sensing rising edge transitions on RXx/DTx, information with any state changes before the Stop bit may signal a false End-of-Character (EOC) and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices or 000h (12 bits) for LIN bus.
PIC18F87J50 FAMILY 20.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTAx<3> and TXSTAx<5>) are set while the Transmit Shift Register is loaded with data.
PIC18F87J50 FAMILY 20.3 EUSART Synchronous Master Mode Once the TXREGx register transfers the data to the TSR register (occurs in one TCY), the TXREGx is empty and the TXxIF flag bit is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXxIE. TXxIF is set regardless of the state of enable bit, TXxIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREGx register.
PIC18F87J50 FAMILY FIGURE 20-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX1/DT1 pin bit 0 bit 1 bit 2 bit 6 bit 7 RC6/TX1/CK1 pin Write to TXREG1 reg TX1IF bit TRMT bit TXEN bit Note: This example is equally applicable to EUSART2 (RG1/TX2/CK2 and RG2/RX2/DT2).
PIC18F87J50 FAMILY 20.3.2 EUSART SYNCHRONOUS MASTER RECEPTION Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTAx<5>) or the Continuous Receive Enable bit, CREN (RCSTAx<4>). Data is sampled on the RXx pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.
PIC18F87J50 FAMILY TABLE 20-8: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF
PIC18F87J50 FAMILY TABLE 20-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 4 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4I
PIC18F87J50 FAMILY TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF
PIC18F87J50 FAMILY 21.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 8 inputs for the 64-pin devices and 12 for the 80-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. The module has six registers: The ADCON0 register, shown in Register 21-1, controls the operation of the A/D module.
PIC18F87J50 FAMILY REGISTER 21-2: ADCON1: A/D CONTROL REGISTER 1(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCAL ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 ADCAL: A/D Calibration bit x = Bit is unknown 1 = Calibration is performed on next A/D
PIC18F87J50 FAMILY The ANCON0 and ANCON1 registers are used to configure the operation of the I/O pin associated with each analog channel. Setting any one of the PCFG bits configures the corresponding pin to operate as a digital only I/O. Clearing a bit configures the pin to operate as an analog input for either the A/D Converter or the comparator module; all digital peripherals are disabled, and digital inputs read as ‘0’.
PIC18F87J50 FAMILY The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0<1>) is cleared and A/D Interrupt Flag bit, ADIF, is set. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode.
PIC18F87J50 FAMILY After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 21.1 “A/D Acquisition Requirements”. After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion.
PIC18F87J50 FAMILY 21.1 A/D Acquisition Requirements For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 21-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F87J50 FAMILY 21.2 Selecting and Configuring Automatic Acquisition Time The ADCON1 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F87J50 FAMILY 21.5 A/D Conversions 21.6 Figure 21-3 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. An A/D conversion can be started by the “Special Event Trigger” of the ECCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as ‘1011’ and that the A/D module is enabled (ADON bit is set).
PIC18F87J50 FAMILY 21.7 A/D Converter Calibration The A/D Converter in the PIC18F87J10 family of devices includes a self-calibration feature which compensates for any offset generated within the module. The calibration process is automated and is initiated by setting the ADCAL bit (ADCON1<6>). The next time the GO/DONE bit is set, the module will perform a “dummy” conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for the offset.
PIC18F87J50 FAMILY TABLE 21-2: Name INTCON SUMMARY OF A/D REGISTERS Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 61 PIR1 PMPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 64 PIE1 PMPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 64 IPR1 PMPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 64 PIR2 OSCFIF CM2IF CM1IF USBIF BCL1IF LVDIF TMR3IF CCP2IF 64 PIE2 OSCFIE CM2IE
PIC18F87J50 FAMILY 22.0 UNIVERSAL SERIAL BUS (USB) 22.1 PIC18F87J10 family devices contain a full-speed and low-speed, compatible USB Serial Interface Engine (SIE) that allows fast communication between any USB host and the PIC® microcontroller. The SIE can be interfaced directly to the USB, utilizing the internal transceiver. This section describes the details of the USB peripheral. Because of the very specific nature of the module, knowledge of USB is expected.
PIC18F87J50 FAMILY 22.2 USB Status and Control In addition, the USB Control register contains a status bit, SE0 (UCON<5>), which is used to indicate the occurrence of a single-ended zero on the bus. When the USB module is enabled, this bit should be monitored to determine whether the differential data lines have come out of a single-ended zero condition. This helps to differentiate the initial power-up state from the USB Reset signal.
PIC18F87J50 FAMILY The PPBRST bit (UCON<6>) controls the Reset status when Double-Buffering mode (ping-pong buffering) is used. When the PPBRST bit is set, all Ping-Pong Buffer Pointers are set to the Even buffers. PPBRST has to be cleared by firmware. This bit is ignored in buffering modes not using ping-pong buffering. The PKTDIS bit (UCON<4>) is a flag indicating that the SIE has disabled packet transmission and reception.
PIC18F87J50 FAMILY REGISTER 22-2: R/W-0 UCFG: USB CONFIGURATION REGISTER U-0 UTEYE — U-0 — R/W-0 UPUEN R/W-0 (1,2) UTRDIS (1) R/W-0 (1) FSEN R/W-0 R/W-0 PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled bit 6 Unimplemented: Always should be programmed to ‘
PIC18F87J50 FAMILY 22.2.2.2 Internal Pull-up Resistors The PIC18F87J10 family devices have built-in pull-up resistors designed to meet the requirements for low-speed and full-speed USB. The UPUEN bit (UCFG<4>) enables the internal pull-ups. Figure 22-1 shows the pull-ups and their control. Note: 22.2.2.3 The official USB specifications require that USB devices must never source any current onto the +5V VBUS line of the USB cable.
PIC18F87J50 FAMILY 22.2.3 USB STATUS REGISTER (USTAT) Clearing the transfer complete flag bit, TRNIF, causes the SIE to advance the FIFO. If the next data in the FIFO holding register is valid, the SIE will reassert the interrupt within 6 TCY of clearing TRNIF. If no additional data is present, TRNIF will remain clear; USTAT data will no longer be reliable. The USB Status register reports the transaction status within the SIE.
PIC18F87J50 FAMILY 22.2.4 USB ENDPOINT CONTROL Each of the 16 possible bidirectional endpoints has its own independent control register, UEPn (where ‘n’ represents the endpoint number). Each register has an identical complement of control bits. The prototype is shown in Register 22-4. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using isochronous endpoints.
PIC18F87J50 FAMILY 22.2.5 USB ADDRESS REGISTER (UADDR) FIGURE 22-4: The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support. 22.2.6 22.
PIC18F87J50 FAMILY 22.4 Buffer Descriptors and the Buffer Descriptor Table The registers in Bank 4 are used specifically for endpoint buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the USB RAM space.
PIC18F87J50 FAMILY The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. No hardware mechanism exists to block access when the UOWN bit is set. Thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller. 22.4.1.
PIC18F87J50 FAMILY REGISTER 22-5: R/W-x UOWN(1) BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE) R/W-x U-0 U-0 (2) (3) (3) DTS — — R/W-x R/W-x R/W-x R/W-x DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its corre
PIC18F87J50 FAMILY 22.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 22-6. Once UOWN is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. The BDnSTAT register is updated by the SIE with the token Packet Identifier (PID) which is stored in BDnSTAT<5:3>.
PIC18F87J50 FAMILY 22.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD.
PIC18F87J50 FAMILY TABLE 22-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 0 (No Ping-Pong) Endpoint Mode 1 (Ping-Pong on EP0 OUT) Mode 3 (Ping-Pong on all other EPs, except EP0) Mode 2 (Ping-Pong on all EPs) Out In Out In Out In Out 0 0 1 0 (E), 1 (O) 1 2 3 3 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) In 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O)
PIC18F87J50 FAMILY 22.5 USB Interrupts Figure 22-7 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the UIE and UIR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the UEIR and UEIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level.
PIC18F87J50 FAMILY 22.5.1 USB INTERRUPT STATUS REGISTER (UIR) Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a ‘0’. The flag bits can also be set in software which can aid in firmware debugging. The USB Interrupt Status register (Register 22-7) contains the flag bits for each of the USB status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register.
PIC18F87J50 FAMILY 22.5.1.1 Bus Activity Detect Interrupt Bit (ACTVIF) The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend or while the USB module is suspended. A few clock cycles are required to synchronize the internal hardware state machine before the ACTVIF bit can be cleared by firmware. Clearing the ACTVIF bit before the internal hardware is synchronized may not have an effect on the value of ACTVIF.
PIC18F87J50 FAMILY 22.5.2 USB INTERRUPT ENABLE REGISTER (UIE) The USB Interrupt Enable register (Register 22-8) contains the enable bits for the USB status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 22-8: The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic.
PIC18F87J50 FAMILY 22.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 22-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic.
PIC18F87J50 FAMILY 22.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE) As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. The USB Error Interrupt Enable register (Register 22-10) contains the enable bits for each of the USB error interrupt sources.
PIC18F87J50 FAMILY 22.6 USB Power Modes 22.6.2 Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here. Also provided is a means of estimating the current consumption of the USB transceiver. 22.6.
PIC18F87J50 FAMILY 22.6.3 DUAL POWER WITH SELF-POWER DOMINANCE 22.6.4 USB TRANSCEIVER CURRENT CONSUMPTION Some applications may require a dual power option. This allows the application to use internal power primarily, but switch to power from the USB when no internal power is available. Figure 22-11 shows a simple Dual Power with Self-Power Dominance mode example, which automatically switches between Self-Power Only and USB Bus Power Only modes.
PIC18F87J50 FAMILY EQUATION 22-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = (60 mA • VUSB • PZERO • PIN • LCABLE) + IPULLUP (3.3V • 5m) Legend: VUSB – Voltage applied to the VUSB pin in volts. (Should be 3.0V to 3.6V.) PZERO – Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’. PIN – Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE – Length (in meters) of the USB cable. The USB 2.
PIC18F87J50 FAMILY 22.7 Oscillator 22.8 The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. Available clocking options are described in detail in Section 2.3 “Oscillator Settings for USB”. TABLE 22-4: Name INTCON USB Firmware and Drivers Microchip provides a number of application-specific resources, such as USB firmware and driver support.
PIC18F87J50 FAMILY 22.9 Overview of USB 22.9.3 This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www.usb.org).
PIC18F87J50 FAMILY The USB specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested, up to a maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit load or less, if necessary.
PIC18F87J50 FAMILY 23.0 COMPARATOR MODULE The analog comparator module contains two comparators that can be independently configured in a variety of ways. The inputs can be selected from the analog inputs and two internal voltage references. The digital outputs are available at the pin level and can also be read through the control register. Multiple output and interrupt event generation are also available. A generic single comparator from the module is shown in Figure 23-1. 23.
PIC18F87J50 FAMILY REGISTER 23-1: CMxCON: COMPARATOR CONTROL x REGISTER R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CON COE CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 6 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin
PIC18F87J50 FAMILY REGISTER 23-2: CMSTAT: COMPARATOR STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-1 R-1 — — — — — — COUT2 COUT1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 COUT2:COUT1: Comparator x Status bits If CPOL = 0 (non-inverted polarity): 1 = Comparator’s VIN+ > VIN0 = Comparator’s VIN+ < VINIf CPOL = 1 (inverted polarity): 1 = Comp
PIC18F87J50 FAMILY 23.2 Comparator Operation 23.3 Comparator Response Time A single comparator is shown in Figure 23-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC18F87J50 FAMILY 23.5 Comparator Control and Configuration Each comparator has up to eight possible combinations of inputs: up to four external analog inputs, and one of two internal voltage references. Both comparators allow a selection of the signal from pin, CxINA, or the voltage from the comparator reference (CVREF) on the non-inverting channel. This is compared to either CxINB, CxINC, CXIND or the microcontroller’s fixed internal reference voltage (VIRV, 1.2V nominal) on the inverting channel.
PIC18F87J50 FAMILY FIGURE 23-4: COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx COE VIN- Cx VIN+ Off (Read as ‘0’) Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CxOUT pin Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE CxINB CxINA COE VINVIN+ Cx CxOUT pin Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 10 CxINC VIN- CxINA VIN+ Cx CxOUT pin Comparator VIRV > CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 11
PIC18F87J50 FAMILY 23.6 Comparator Interrupts The comparator interrupt flag is set whenever any of the following occurs: - Low-to-high transition of the comparator output - High-to-low transition of the comparator output - Any change in the comparator output. The comparator interrupt selection is done by the EVPOL1:EVPOL0 bits in the CMxCON register (CMxCON<4:3>). In order to provide maximum flexibility, the output of the comparator may be inverted using the CPOL bit in the CMxCON register (CMxCON<5>).
PIC18F87J50 FAMILY 23.7 Comparator Operation During Sleep 23.8 A device Reset forces the CMxCON registers to their Reset state. This forces both comparators and the voltage reference to the OFF state. When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from Sleep mode, when enabled. Each operational comparator will consume additional current.
PIC18F87J50 FAMILY 24.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. FIGURE 24-1: A block diagram of the module is shown in Figure 24-1.
PIC18F87J50 FAMILY 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution.
PIC18F87J50 FAMILY 24.2 Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 24-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 28.
PIC18F87J50 FAMILY NOTES: DS39775C-page 348 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY 25.0 SPECIAL FEATURES OF THE CPU PIC18F87J10 family devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F87J50 FAMILY TABLE 25-1: MAPPING OF THE FLASH CONFIGURATION WORDS TO THE CONFIGURATION REGISTERS Configuration Byte Code Space Address Configuration Register Address XXXF8h 300000h CONFIG1L CONFIG1H XXXF9h 300001h CONFIG2L XXXFAh 300002h CONFIG2H XXXFBh 300003h CONFIG3L XXXFCh 300004h CONFIG3H XXXFDh 300005h CONFIG4L(1) XXXFEh 300006h CONFIG4H(1) XXXFFh 300007h Note 1: Unimplemented in PIC18F87J10 family devices.
PIC18F87J50 FAMILY REGISTER 25-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW (BYTE ADDRESS 300000h) R/WO-1 R/WO-1 R/WO-1 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 DEBUG XINST STVREN — PLLDIV2 PLLDIV1 PLLDIV0 WDTEN bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled; RB6 and RB7 configured as general purpo
PIC18F87J50 FAMILY REGISTER 25-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) U-1 U-1 U-1 U-1 U-0 R/WO-1 R/WO-1 R/WO-1 — — — — — CP0 CPDIV1 CPDIV0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Maintain as ‘1’ bit 3 Unimplemented: Read as ‘0’ bit 2 CP0: Code Protection bit 1 = Program memory is not code-protected 0 = Program memory is c
PIC18F87J50 FAMILY REGISTER 25-3: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) R/WO-1 R/WO-1 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 IESO FCMEN — — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up
PIC18F87J50 FAMILY REGISTER 25-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1
PIC18F87J50 FAMILY REGISTER 25-5: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 WAIT(1) BW(1) EMB1(1) EMB0(1) EASHFT(1) — — — bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WAIT: External Bus Wait Enable bit(1) 1 = Wait states on the external bus are disabled 0 = Wait states on the external bus
PIC18F87J50 FAMILY REGISTER 25-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) U-1 U-1 U-1 U-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1 — — — — MSSPMSK PMPMX(1) ECCPMX(1) CCP2MX bit 7 bit 0 Legend: R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Maintain as ‘1’ bit 3 MSSPMSK: MSSP V3’s 7-Bit Address Masking Mode Enable bit 1 = 7-Bit Address Masking mode
PIC18F87J50 FAMILY REGISTER 25-7: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F87J50 FAMILY DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 DEV2:DEV0: Device ID bits(1) 111 = PIC18F86J50 110 = reserved 101 = PIC18F85J50 100 = PIC18F67J50 011 = PIC18F66J55 010 = PIC18F66J50 001 = PIC18F87J50 000 = PIC18F65J50 and PIC18F86
PIC18F87J50 FAMILY 25.2 Watchdog Timer (WDT) 25.2.1 For PIC18F87J10 family devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexor, controlled by the WDTPS bits in Configuration Register 2H.
PIC18F87J50 FAMILY REGISTER 25-9: WDTCON: WATCHDOG TIMER CONTROL REGISTER R/W-0 R-x U-0 R/W-0 U-0 U-0 U-0 U-0 REGSLP(2) LVDSTAT — ADSHR — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REGSLP: Voltage Regulator Low-Power Operation Enable bit(2) bit 7 1 = On-chip regulator enters low-power operation when device enters Sleep mode 0 = On-chip regulator
PIC18F87J50 FAMILY 25.3 On-Chip Voltage Regulator All of the PIC18F87J10 family devices power their core digital logic at a nominal 2.5V. For designs that are required to operate at a higher typical voltage, such as 3.3V, all devices in the PIC18F87J10 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins.
PIC18F87J50 FAMILY 25.3.2 ON-CHIP REGULATOR AND BOR Substantial Sleep mode power savings can be obtained by setting the REGSLP bit, but device wake-up time will increase in order to insure the regulator has enough time to stabilize. The REGSLP bit is automatically cleared by hardware when a Low-Voltage Detect condition occurs. When the on-chip regulator is enabled, PIC18F87J10 family devices also have a simple brown-out capability.
PIC18F87J50 FAMILY 25.4.1 SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP While using the INTRC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 3.1.4 “Multiple Sleep Commands”). In practice, this means that user code can change the SCS1:SCS0 bit settings or issue SLEEP instructions before the OST times out.
PIC18F87J50 FAMILY FIGURE 25-5: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Clock Monitor Test Note: 25.5.2 Clock Monitor Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode.
PIC18F87J50 FAMILY 25.6 Program Verification and Code Protection For all devices in the PIC18F87J10 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, CP0. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. 25.6.
PIC18F87J50 FAMILY 26.0 INSTRUCTION SET SUMMARY The PIC18F87J10 family of devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 26.
PIC18F87J50 FAMILY TABLE 26-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F87J50 FAMILY FIGURE 26-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
PIC18F87J50 FAMILY TABLE 26-2: PIC18F87J50 FAMILY INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a
PIC18F87J50 FAMILY TABLE 26-2: PIC18F87J50 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18F87J50 FAMILY TABLE 26-2: PIC18F87J50 FAMILY INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Sub
PIC18F87J50 FAMILY 26.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F87J50 FAMILY ADDWFC ADD W and Carry bit to f ANDLW AND Literal with W Syntax: ADDWFC Syntax: ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) + (f) + (C) → dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F87J50 FAMILY ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 Description: Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Encoding: 01da ffff ffff 1110 Description: The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F87J50 FAMILY BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] f, b {,a} Operation: 0 → f Status Affected: None Encoding: 1001 Description: Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F87J50 FAMILY BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0011 nnnn nnnn If the Carry bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F87J50 FAMILY BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ n n Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 Description: 0101 nnnn nnnn If the Overflow bit is ‘0’, then the program will branch. Encoding: 1110 Description: The 2’s complement number ‘2n’ is added to the PC.
PIC18F87J50 FAMILY BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: n 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F87J50 FAMILY BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F87J50 FAMILY BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: 0111 Description: Encoding: bbba ffff ffff 1110 Description: Bit ‘b’ in data memory location ‘f’ is inverted.
PIC18F87J50 FAMILY BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} n Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: Status Affected: None (PC) + 4 → TOS, k → PC<20:1>; if s = 1, (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F87J50 FAMILY CLRF Clear f Syntax: CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: 000h → f, 1→Z Status Affected: Z Encoding: 0110 Description: 101a ffff ffff Clears the contents of the specified register.
PIC18F87J50 FAMILY COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: f → dest Status Affected: N, Z Encoding: 0001 Description: 11da ffff ffff The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F87J50 FAMILY CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by
PIC18F87J50 FAMILY DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 → W<3:0>; else, (W<3:0>) → W<3:0> 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> > 9] or [C = 1] then, (W<7:4>) + 6 → W<7:4>, C = 1; else, (W<7:4>) → W<7:4> Status Affected: 0000 Description: C Encoding: 0000 0000 0000 DAW adjusts the
PIC18F87J50 FAMILY DECFSZ Decrement f, Skip if 0 DCFSNZ Decrement f, Skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F87J50 FAMILY GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Description: GOTO allows an unconditional branch anywhere within entire 2-Mbyte memory range.
PIC18F87J50 FAMILY INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f {,d {,a}} Increment f, Skip if not 0 f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented.
PIC18F87J50 FAMILY IORLW Inclusive OR Literal with W IORWF Inclusive OR W with f Syntax: IORLW k Syntax: IORWF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) .OR. k → W Status Affected: N, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z Encoding: 0000 1001 kkkk kkkk Description: The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F87J50 FAMILY LFSR Load FSR MOVF Move f Syntax: LFSR f, k Syntax: MOVF Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F87J50 FAMILY MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR Status Affected: None Operation: (fs) → fd Status Affected: None Encoding: 1st word (source) 2nd word (destin.) Encoding: 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F87J50 FAMILY MOVLW Move Literal to W MOVWF Move W to f Syntax: MOVLW k Syntax: MOVWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Encoding: 0000 Description: 1110 kkkk kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F87J50 FAMILY MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: 0000 Description: 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair.
PIC18F87J50 FAMILY NEGF Negate f Syntax: NEGF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] f {,a} Operation: (f) + 1 → f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 110a ffff If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f ≤ 95 (5Fh). See Section 26.2.3 “Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode” for details.
PIC18F87J50 FAMILY POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F87J50 FAMILY RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET n Operands: -1024 ≤ n ≤ 1023 Operands: None Operation: (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F87J50 FAMILY RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 Description: 0000 0001 Words: 1 Cycles: 2 Q Cycle Activity: kkkk kkkk W is loaded with th
PIC18F87J50 FAMILY RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: RETURN {s} Syntax: RLCF Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC; if s = 1, (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Description: Encoding: 0000 0001 001s 0011 Description: Return from subroutine.
PIC18F87J50 FAMILY RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F87J50 FAMILY RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> Status Affected: N, Z Encoding: 0100 Description: f {,d {,a}} 00da Operation: FFh → f Status Affected: None Encoding: ffff ffff 0110 Description: The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F87J50 FAMILY SLEEP Enter Sleep Mode SUBFWB Subtract f from W with Borrow Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 0101 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F87J50 FAMILY SUBLW Subtract W from Literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F87J50 FAMILY SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F87J50 FAMILY TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT, (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR, (Prog Mem (TBLPTR)) → TABLAT Before Instruction TABLAT TBLPTR MEMORY(00A356h) After Instruction TABLAT TBLPTR Example 2: Status Af
PIC18F87J50 FAMILY TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) → Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register, (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register, (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR, (TABLAT) → Holding Register Status Affected: Example 2: None Encoding: Description: Before Instruction TABLAT = 55h TBLPTR = 00
PIC18F87J50 FAMILY TSTFSZ Test f, Skip if 0 XORLW Exclusive OR Literal with W Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → W Status Affected: N, Z Operation: skip if f = 0 Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F87J50 FAMILY XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 Description: f {,d {,a}} 10da ffff ffff Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18F87J50 FAMILY 26.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 26-3. Detailed descriptions are provided in Section 26.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 26-1 (page 366) apply to both the standard and extended PIC18 instruction sets.
PIC18F87J50 FAMILY 26.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operands: 0 ≤ k ≤ 63 Operation: FSR(f) + k → FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k → FSR2, Operation: (TOS) → PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F87J50 FAMILY CALLW Subroutine Call using WREG MOVSF Move Indexed to f Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU 0 ≤ zs ≤ 127 0 ≤ fd ≤ 4095 Operation: ((FSR2) + zs) → fd Status Affected: None Status Affected: None Encoding: 0000 Description 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack.
PIC18F87J50 FAMILY MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 ≤ zs ≤ 127 0 ≤ zd ≤ 127 Operands: 0 ≤ k ≤ 255 Operation: k → (FSR2), FSR2 – 1 → FSR2 Status Affected: None Operation: ((FSR2) + zs) → ((FSR2) + zd) Status Affected: None Encoding: 1st word (source) 2nd word (dest.
PIC18F87J50 FAMILY SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 ≤ k ≤ 63 Operands: 0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ] Operation: FSR2 – k → FSR2, Operation: FSRf – k → FSRf Status Affected: None Encoding: 1110 (TOS) → PC Status Affected: 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F87J50 FAMILY 26.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing (Section 5.6.1 “Indexed Addressing with Literal Offset”).
PIC18F87J50 FAMILY ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 ≤ k ≤ 95 d ∈ [0,1] Operands: 0 ≤ f ≤ 95 0≤b≤7 Operation: (W) + ((FSR2) + k) → dest Operation: 1 → ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None ADDWF Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the valu
PIC18F87J50 FAMILY 26.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set for the PIC18F87J10 family. This includes the MPLAB C18 C Compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F87J50 FAMILY 27.
PIC18F87J50 FAMILY 27.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC18F87J50 FAMILY 27.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18F87J50 FAMILY 27.11 PICSTART Plus Development Programmer 27.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC18F87J50 FAMILY 28.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ....................................
PIC18F87J50 FAMILY FIGURE 28-1: PIC18F87J50 FAMILY VDD FREQUENCY GRAPH (INDUSTRIAL) 4.0V 3.6V Voltage (VDD) 3.5V (Note 1) 3.0V PIC18F87J50 Family 2.5V 2.35V 2.0V 48 MHz 8 MHz 0 Frequency Note 1: When the USB module is enabled, VUSB and VDD should be connected together and provided 3.0V-3.6V while VDDCORE must be ≥ 2.45V. When the core regulator is enabled and VDD is ≥ 3.0V, it will always regulate to ≥ 2.45V.
PIC18F87J50 FAMILY 28.1 DC Characteristics: Supply Voltage PIC18F87J50 Family (Industrial) PIC18F87J50 Family (Industrial) Param No. Symbol Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Characteristic Supply Voltage Min Typ Max Units Conditions VDDCORE 2.0 — — 3.6 3.6 V V ENVREG = 0 ENVREG = 1 2.0 — 2.75 V ENVREG = 0 VDD – 0.3 — VDD + 0.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 0.5 1.4 μA -40°C 0.5 1.4 μA +25°C 5.5 10.2 μA +85°C 0.6 1.5 μA -40°C 0.6 1.5 μA +25°C 6.8 12.6 μA +85°C 2.9 7 μA -40°C 3.6 7 μA +25°C 9.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 5 14.2 μA -40°C 5.5 14.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 3 9.4 μA -40°C 3.3 9.4 μA +25°C 8.5 17.2 μA +85°C 4 10.5 μA -40°C 4.3 10.5 μA +25°C 10.3 19.5 μA +85°C 34 82 μA -40°C 48 82 μA +25°C 69 105 μA +85°C 0.33 0.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 0.17 0.35 mA -40°C 0.18 0.35 mA +25°C +85°C Supply Current (IDD) Cont.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 4.5 5.2 mA -40°C 4.4 5.2 mA +25°C 4.5 5.2 mA +85°C 5.7 6.7 mA -40°C 5.5 6.3 mA +25°C +85°C Supply Current (IDD) Cont.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 0.10 0.26 mA -40°C 0.07 0.18 mA +25°C +85°C Supply Current (IDD) Cont.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. Power-Down and Supply Current PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device Typ Max Units Conditions 18 35 µA -40°C 19 35 µA +25°C 28 49 µA +85°C 20 45 µA -40°C 21 45 µA +25°C +85°C Supply Current (IDD) Cont.
PIC18F87J50 FAMILY 28.2 DC Characteristics: PIC18F87J50 Family (Industrial) Param No. D022 (ΔIWDT) D025 (ΔIOSCB) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Device D027 (ΔIUSB) Note 1: 2: 3: 4: 5: 6: Typ Max Units Conditions Module Differential Currents (ΔIWDT, ΔIOSCB, ΔIAD, ΔIUSB) Watchdog Timer 2.1 7.
PIC18F87J50 FAMILY 28.3 DC Characteristics:PIC18F87J50 Family (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions Input Low Voltage All I/O ports: D030 with TTL buffer VSS 0.15 VDD V D031 with Schmitt Trigger buffer VSS 0.2 VDD V D032 MCLR VSS 0.2 VDD V D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes D033A OSC1 VSS 0.
PIC18F87J50 FAMILY 28.3 DC Characteristics:PIC18F87J50 Family (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. Min Max Units PORTA, PORTF, PORTG, PORTH(3) — 0.4 V IOL = 2 mA, VDD = 3.3V, -40°C to +85°C PORTD, PORTE, PORTJ(3) — 0.4 V IOL = 3.4 mA, VDD = 3.3V, -40°C to +85°C PORTB, PORTC — 0.4 V IOL = 3.4 mA, VDD = 3.
PIC18F87J50 FAMILY TABLE 28-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Program Flash Memory D130 EP Cell Endurance 10K — — D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum operating voltage D132B VPEW VDD for Self-Timed Write VMIN — 3.
PIC18F87J50 FAMILY TABLE 28-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — AVDD – 1.5 V (2) VIRV Internal Reference Voltage — ±1.
PIC18F87J50 FAMILY TABLE 28-5: USB MODULE SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param No. Sym Characteristics Min Typ Max Units Comments D313 VUSB USB Voltage 3.0 — 3.6 V Voltage on VUSB pin must be in this range for proper USB operation D314 IIL Input Leakage on pin — — ±1 μA VSS < VPIN < VDD pin at high impedance D315 VILUSB Input Low Voltage for USB Buffer — — 0.
PIC18F87J50 FAMILY 28.4 28.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F87J50 FAMILY 28.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 28-6 apply to all timing specifications unless otherwise noted. Figure 28-3 specifies the load conditions for the timing specifications. TABLE 28-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 28-3: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Operating voltage VDD range as described in Section 28.1 and Section 28.3.
PIC18F87J50 FAMILY 28.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 28-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 28-7: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 48 MHz DC 48 4 25 4 25 20.8 — 20.8 — 40.0 250 40.
PIC18F87J50 FAMILY TABLE 28-8: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V) Sym Characteristic F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (lock time) ΔCLK CLKO Stability (jitter) F13 Min Typ† Max Units 4 — — 96 48 — MHz MHz — — 2 ms -0.25 — +0.25 % Conditions † Data in “Typ” column is at 3.3V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC18F87J50 FAMILY FIGURE 28-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 19 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 28-3 for load conditions. TABLE 28-10: CLKO AND I/O TIMING REQUIREMENTS Param No.
PIC18F87J50 FAMILY FIGURE 28-6: PROGRAM MEMORY READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 AD<15:0> Address Address Address Data from External 150 151 Address 163 160 162 161 155 166 167 ALE 168 164 169 171 CE 171A OE 165 Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-11: PROGRAM MEMORY READ TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 0.
PIC18F87J50 FAMILY FIGURE 28-7: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:16> BA0 Address Address 166 AD<15:0> Data Address Address 153 150 156 151 ALE 171 CE 171A 154 WRH or WRL 157A 157 UB or LB Operating Conditions: 2.0V < VCC < 3.6V, -40°C < TA < +125°C unless otherwise stated. TABLE 28-12: PROGRAM MEMORY WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units 0.
PIC18F87J50 FAMILY FIGURE 28-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 28-3 for load conditions. TABLE 28-13: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Typ Max Units Conditions 2 — — μs 3.4 4.0 4.
PIC18F87J50 FAMILY FIGURE 28-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T13CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 28-3 for load conditions. TABLE 28-14: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F87J50 FAMILY FIGURE 28-10: CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 28-3 for load conditions. TABLE 28-15: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULES) Param Symbol No. 50 51 TCCL TCCH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18F87J50 FAMILY FIGURE 28-11: PARALLEL MASTER PORT READ TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 System Clock PMA<13:18> PMD<7:0> Address Address<7:0> Data PM6 PM2 PM7 PM3 PMRD PM5 PMWR PMALL/PMALH PM1 PMCS<2:1> Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-16: PARALLEL MASTER PORT READ TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units PM1 PMALL/PMALH Pulse Width — 0.
PIC18F87J50 FAMILY FIGURE 28-12: PARALLEL MASTER PORT WRITE TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 System Clock PMA<13:18> PMD<7:0> Address Address<7:0> Data PM12 PM13 PMRD PMWR PM11 PMALL/ PMALH PMCS<2:1> PM16 Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C unless otherwise stated. TABLE 28-17: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS Param. No Symbol Characteristics Min Typ Max Units PM11 PMWR Pulse Width — 0.
PIC18F87J50 FAMILY FIGURE 28-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 71 72 78 79 79 78 SCKx (CKP = 1) 80 bit 6 - - - - - - 1 MSb SDOx LSb 75, 76 SDIx MSb In bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 28-3 for load conditions. TABLE 28-18: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No.
PIC18F87J50 FAMILY FIGURE 28-14: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SSx 81 SCKx (CKP = 0) 71 72 79 73 SCKx (CKP = 1) 80 78 MSb SDOx bit 6 - - - - - - 1 LSb bit 6 - - - - 1 LSb In 75, 76 SDIx MSb In 74 Note: Refer to Figure 28-3 for load conditions. TABLE 28-19: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18F87J50 FAMILY FIGURE 28-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SSx 70 SCKx (CKP = 0) 83 71 72 78 79 79 78 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 MSb In SDIx SDI 77 bit 6 - - - - 1 LSb In 74 73 Note: Refer to Figure 28-3 for load conditions. TABLE 28-20: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param No.
PIC18F87J50 FAMILY FIGURE 28-16: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SSx SCKx (CKP = 0) 70 83 71 72 73 SCKx (CKP = 1) 80 MSb SDOx bit 6 - - - - - - 1 LSb 75, 76 SDIx SDI Note: MSb In 77 bit 6 - - - - 1 LSb In 74 Refer to Figure 28-3 for load conditions. TABLE 28-21: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No.
PIC18F87J50 FAMILY FIGURE 28-17: I2C™ BUS START/STOP BITS TIMING SCLx 91 93 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-3 for load conditions. TABLE 28-22: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18F87J50 FAMILY TABLE 28-23: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH 101 TLOW 102 TR Characteristic Clock High Time Clock Low Time Min Max Units 100 kHz mode 4.0 — μs 400 kHz mode 0.6 — μs MSSP modules 1.5 TCY — 100 kHz mode 4.7 — μs μs 400 kHz mode 1.3 — MSSP modules 1.5 TCY — — 1000 ns 20 + 0.
PIC18F87J50 FAMILY FIGURE 28-19: MSSPx I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCLx 93 91 90 92 SDAx Stop Condition Start Condition Note: Refer to Figure 28-3 for load conditions. TABLE 28-24: MSSPx I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18F87J50 FAMILY TABLE 28-25: MSSPx I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 101 THIGH TLOW Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms (1) 2(TOSC)(BRG + 1) — ms — 1000 ns 20 + 0.
PIC18F87J50 FAMILY FIGURE 28-21: EUSARTx SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 28-3 for load conditions. TABLE 28-26: EUSARTx SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F87J50 FAMILY TABLE 28-28: A/D CONVERTER CHARACTERISTICS: PIC18F87J50 FAMILY (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units — — 10 bit Conditions ΔVREF ≥ 3.0V A01 NR Resolution A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A04 EDL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V A06 EOFF Offset Error — — <±3 LSb ΔVREF ≥ 3.0V A07 EGN Gain Error — — <±3 LSb ΔVREF ≥ 3.
PIC18F87J50 FAMILY TABLE 28-29: A/D CONVERSION REQUIREMENTS Param Symbol No. Characteristic Min Max Units 25.0(1) μs TOSC based, VREF ≥ 3.0V A/D RC mode 130 TAD A/D Clock Period 0.7 — 1 μs 131 TCNV Conversion Time (not including acquisition time)(2) 11 12 TAD 132 TACQ Acquisition Time(3) 1.4 — μs 135 TSWC Switching Time from Convert → Sample — (Note 4) 137 TDIS Discharge Time 0.
PIC18F87J50 FAMILY FIGURE 28-24: USB SIGNAL TIMING USB Data Differential Lines 90% VCRS 10% TLF, TFF TLR, TFR TABLE 28-30: USB LOW-SPEED TIMING REQUIREMENTS Param No. Symbol Characteristic Min Typ Max Units Conditions TLR Transition Rise Time 75 — 300 ns CL = 200 to 600 pF TLF Transition Fall Time 75 — 300 ns CL = 200 to 600 pF TLRFM Rise/Fall Time Matching 80 — 125 % Min Typ Max Units TABLE 28-31: USB FULL-SPEED REQUIREMENTS Param No.
PIC18F87J50 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 80-Lead TQFP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18F87J50 FAMILY 29.2 Package Details The following sections give the technical details of the packages. 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC18F87J50 FAMILY 80-Lead Plastic Thin Quad Flatpack (PT) – 12x12x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 12 3 α NOTE 2 A c β φ A2 A1 L1 L Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 80 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.05 – 0.
PIC18F87J50 FAMILY NOTES: DS39775C-page 462 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (February 2007) DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1, Original data sheet for the PIC18F87J10 family of devices. Revision B (May 2007) Updated electrical specification data. Revision C (October 2009) Removed “Preliminary” marking.
PIC18F87J50 FAMILY NOTES: DS39775C-page 464 © 2009 Microchip Technology Inc.
PIC18F87J50 FAMILY INDEX A A/D ................................................................................... 301 A/D Converter Interrupt, Configuring ....................... 305 Acquisition Requirements ........................................ 306 ADCAL Bit ................................................................ 309 ADRESH Register .................................................... 304 Analog Port Pins, Configuring .................................. 307 Associated Registers ................
PIC18F87J50 FAMILY Detecting .................................................................... 57 Disabling in Sleep Mode ............................................ 57 BSF .................................................................................. 377 BTFSC ............................................................................. 378 BTFSS .............................................................................. 378 BTG ...................................................................
PIC18F87J50 FAMILY PIC18F87J50 Family Devices ........................... 79 Shared Address Registers ................................. 82 Special Function Registers ................................ 81 Special Function Registers ........................................ 81 Context Defined SFRs ....................................... 82 USB RAM ................................................................... 78 DAW .................................................................................
PIC18F87J50 FAMILY Writing ...................................................................... 103 Unexpected Termination .................................. 106 Write Verify ...................................................... 106 FSCM. See Fail-Safe Clock Monitor. G GOTO ............................................................................... 386 H Hardware Multiplier .......................................................... 119 8 x 8 Multiplication Algorithms ...............................
PIC18F87J50 FAMILY RETLW .................................................................... 396 RETURN .................................................................. 397 RLCF ........................................................................ 397 RLNCF ..................................................................... 398 RRCF ....................................................................... 398 RRNCF .................................................................... 399 SETF .........
PIC18F87J50 FAMILY RA4/PMD5/T0CKI ...................................................... 23 RA4/T0CKI ................................................................. 15 RA5/AN4/C2INA ........................................................ 15 RA5/PMD4/AN4/C2INA ............................................. 23 RA6 ...................................................................... 15, 23 RA7 ...................................................................... 15, 23 RB0/FLT0/INT0 .....................
PIC18F87J50 FAMILY PORTG Associated Registers ............................................... 160 LATG Register ......................................................... 158 PORTG Register ...................................................... 158 TRISG Register ........................................................ 158 PORTH Associated Registers ............................................... 163 LATH Register ......................................................... 161 PORTH Register ..................
PIC18F87J50 FAMILY CONFIG1L (Configuration 1 Low) ............................ 351 CONFIG2H (Configuration 2 High) .......................... 354 CONFIG3H (Configuration 3 High) .......................... 356 CONFIG3L (Configuration 3 Low) ...................... 71, 355 CVRCON (Comparator Voltage Reference Control) 346 DEVID1 (Device ID 1) .............................................. 357 DEVID2 (Device ID 2) .............................................. 357 ECCPxAS (ECCPx Auto-Shutdown Control) .........
PIC18F87J50 FAMILY SUBFWB .......................................................................... 400 SUBLW ............................................................................ 401 SUBULNK ........................................................................ 411 SUBWF ............................................................................ 401 SUBWFB .......................................................................... 402 SWAPF ........................................................
PIC18F87J50 FAMILY abled) ............................................................... 230 PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled) ............................................................... 230 PWM Direction Change ........................................... 227 PWM Direction Change at Near 100% Duty Cycle .. 227 PWM Output ............................................................ 214 Read and Write, 8-Bit Data, Demultiplexed Address 183 Read, 16-Bit Data, Demultiplexed Address .....
PIC18F87J50 FAMILY Layered Framework ................................................. 335 Oscillator Requirements ........................................... 334 Overview .......................................................... 311, 335 Ping-Pong Buffer Configuration ............................... 315 Power ....................................................................... 335 Power Modes ........................................................... 331 Bus Power Only ................................
PIC18F87J50 FAMILY NOTES: DS39775C-page 476 © 2009 Microchip Technology Inc.
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PIC18F87J50 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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