User Manual
Hexiwear Workstation
Page 17
Input/Output Group
CONNECTIVITY
One of the most distinctive features of Hexiwear Workstation board are the Input/Output groups. These groups contain buttons, LEDs and headers, routed to the pins of the
docking connector. They allow interaction with the docked Hexiwear, either by pressing buttons, displaying states of its pins on the LEDs, or using headers to interface it to an
external device.
Tri-state DIP switches, like the SW3 on Figure 13, are used to enable
4K7 pull-up or pull-down resistor on any desired pin. Each I/O group
has one such DIP switch, which enables these pull-up/pull-down
resistors on pins of the particular group. These DIP switches can
have three states:
1. MIDDLE POSITION: disconnects both the pull-up and pull-
down resistors from a selected group pin
2. UP POSITION: connects the pull-up resistor to a selected
group pin.
3. DOWN POSITION: connects the pull-down resistor to a
selected group pin.
The pins of the Hexiwear docking connector are arranged in groups. There are 5
groups with 8 pins routed to the Hexiwear docking header, in each. All the pins are
marked with the label that clearly identifies to which group a particular pin belongs: for
example, G1.4 means that the specific pin is the pin number 4 in the I/O group 1. Pins
and groups are labeled starting with 0. This concept makes development easier, and
makes the entire Hexiwear Workstation clean and well organized.
Everything is grouped together
Tri-state pull-up/pull-
down DIP switches
LD2
R17
10k
LD3
R18
10k
LD4
R19
10k
LD5
R20
10k
LD6
R21
10k
LD7
R22
10k
LD8
R23
10k
LD9
R24
10k
G0_LED
G0.1
G0.2
G0.3
G0.4
G0.5
G0.6
G0.7
G0.0
1 2
3 4
5 6
7 8
9 10
J7
R25
4.7k
R26
4.7k
R27
4.7k
R28
4.7k
R29
4.7k
R30
4.7k
R31
4.7k
R32
4.7k
VCC-3V3
VCC-3V3
1 2
3 4
5 6
7 8
9 10
J8
VCC-3V3
1 2 3 4 5 6 7 8
+
_
SW3
G0.1
G0.2
G0.3
G0.4
G0.5
G0.6
G0.0
G0.1
G0.2 G0.3
G0.4 G0.5
G0.6
G0.0
G0.1
G0.2
G0.3
G0.4
G0.5
G0.6
G0.0
G0.7
G0.7 G0.7
G0.2
G0.4
G0.6
G0.0 G0.1
G0.3
G0.5
G0.7
4
5
6
1
2
3
7
8
9
10
J6
M1X10
VCC-3V3
G0_LEVEL
G0.1
G0.2
G0.3
G0.4
G0.5
G0.6
G0.7
G0.0
T1 T2 T3 T4 T5 T6 T7 T8
DATA BUS
Figure 13: I/O group with the schematic