Information

© 2008 Microchip Technology Inc. DS39646C-page 79
PIC18F8722 FAMILY
PORTJ
(2)
RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx xxxx 60, 156
PORTH
(2)
RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 0000 xxxx 60, 154
PORTG
— —RG5
(5)
RG4 RG3 RG2 RG1 RG0 --xx xxxx 60, 151
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 x000 0000 60, 149
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx 60, 146
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 60, 143
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 60, 140
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 60, 137
PORTA RA7
(4)
RA6
(4)
RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 61, 135
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte 0000 0000 61, 252
BAUDCON1 ABDOVF RCIDL
— SCKP BRG16 —WUEABDEN01-0 0-00 61, 250
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte 0000 0000 61, 252
BAUDCON2 ABDOVF RCIDL
— SCKP BRG16 —WUEABDEN01-0 0-00 61, 250
ECCP1DEL P1RSEN P1DC6 P1DC5 P1DC4 P1DC3 P1DC2 P1DC1 P1DC0 0000 0000 61, 200
TMR4 Timer4 Register 0000 0000 61, 178
PR4 Timer4 Period Register 1111 1111 61, 178
T4CON
— T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 61, 178
CCPR4H Capture/Compare/PWM Register 4 High Byte xxxx xxxx 61, 180
CCPR4L Capture/Compare/PWM Register 4 Low Byte xxxx xxxx 61, 180
CCP4CON
— — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 61, 179
CCPR5H Capture/Compare/PWM Register 5 High Byte xxxx xxxx 61, 180
CCPR5L Capture/Compare/PWM Register 5 Low Byte xxxx xxxx 61, 180
CCP5CON
— — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 --00 0000 61, 179
SPBRG2 EUSART2 Baud Rate Generator Register Low Byte 0000 0000 61, 252
RCREG2 EUSART2 Receive Register 0000 0000 61, 260
TXREG2 EUSART2 Transmit Register 0000 0000 61, 257
TXSTA2 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 61, 248
RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 61, 249
ECCP3AS ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 61, 201
ECCP3DEL P3RSEN P3DC6 P3DC5 P3DC4 P3DC3 P3DC2 P3DC1 P3DC0 0000 0000 61, 200
ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 61, 201
ECCP2DEL P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 61, 200
SSP2BUF MSSP2 Receive Buffer/Transmit Register xxxx xxxx 61, 170
SSP2ADD MSSP2 Address Register in I
2
C™ Slave mode. MSSP2 Baud Rate Reload Register in I
2
C Master mode. 0000 0000 61, 170
SSP2STAT SMP CKE D/A
PSR/WUA BF 0000 0000 61, 216
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 61, 217
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 61, 218
TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
2: These registers and/or bits are not implemented on 64-pin devices and are read as
‘0’. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as
‘0’.
6: Bit 7 and Bit 6 are cleared by user software or by a POR.
7: Bit 21 of TBLPTRU allows access to the device Configuration bits.