Information

PIC18F8722 FAMILY
DS39646C-page 78 © 2008 Microchip Technology Inc.
PSPCON IBF OBF IBOV PSPMODE — — — — 0000 ---- 59, 252
SPBRG1 EUSART1 Baud Rate Generator Register Low Byte 0000 0000 59, 252
RCREG1 EUSART1 Receive Register 0000 0000 59, 260
TXREG1 EUSART1 Transmit Register 0000 0000 59, 257
TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 59, 248
RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 59, 249
EEADRH
— — — — — — EEPROM Address
Register High Byte
---- --00 59, 111
EEADR EEPROM Address Register Low Byte 0000 0000 59, 111
EEDATA EEPROM Data Register 0000 0000 59, 111
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 59, 88
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 59, 89
IPR3 SSP2IP BCL2IP RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 1111 1111 60, 131
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 0000 0000 60, 125
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 0000 0000 60, 129
IPR2 OSCFIP CMIP
— EEIP BCL1IP HLVDIP TMR3IP CCP2IP 11-1 1111 60, 131
PIR2 OSCFIF CMIF
— EEIF BCL1IF HLVDIF TMR3IF CCP2IF 00-0 0000 60, 125
PIE2 OSCFIE CMIE
— EEIE BCL1IE HLVDIE TMR3IE CCP2IE 00-0 0000 60, 128
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 1111 1111 60, 130
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 60, 124
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 60, 127
MEMCON
(2)
EBDIS —WAIT1WAIT0— —WM1WM00-00 --00 60, 96
OSCTUNE INTSRC PLLEN
(3)
— TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 35, 60
TRISJ
(2)
TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 1111 1111 60, 157
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 1111 1111 60, 155
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 ---1 1111 60, 153
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 60, 150
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 60, 148
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 60, 143
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 60, 140
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 60, 137
TRISA TRISA7
(4)
TRISA6
(4)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 60, 135
LATJ
(2)
LATJ7LATJ6LATJ5LATJ4LATJ3LATJ2LATJ1LATJ0xxxx xxxx 60, 156
LATH
(2)
LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx xxxx 60, 154
LATG
— —LATG5
(5)
LATG4 LATG3 LATG2 LATG1 LATG0 --xx xxxx 60, 151
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx 60, 149
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx xxxx 60, 146
LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx xxxx 60, 143
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx 60, 140
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx 60, 137
LATA LATA7
(4)
LATA6
(4)
LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx xxxx 60, 135
TABLE 5-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
2: These registers and/or bits are not implemented on 64-pin devices and are read as
‘0’. Reset values are shown for 80-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
3: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
‘0’. See Section 2.6.4 “PLL in
INTOSC Modes”.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
5: RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as
‘0’.
6: Bit 7 and Bit 6 are cleared by user software or by a POR.
7: Bit 21 of TBLPTRU allows access to the device Configuration bits.