Information

© 2008 Microchip Technology Inc. DS39646C-page 61
PIC18F8722 FAMILY
PORTA
(5)
6X27 6X22 8X27 8X22 xx0x 0000
(5)
uu0u 0000
(5)
uuuu uuuu
(5)
SPBRGH1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
BAUDCON1 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu
SPBRGH2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
BAUDCON2 6X27 6X22 8X27 8X22 01-0 0-00 01-0 0-00 uu-u u-uu
ECCP1DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TMR4 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
PR4 6X27 6X22 8X27 8X22 1111 1111 uuuu uuuu uuuu uuuu
T4CON 6X27 6X22 8X27 8X22 -000 0000 -000 0000 -uuu uuuu
CCPR4H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR4L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP4CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
CCPR5H 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR5L 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
CCP5CON 6X27 6X22 8X27 8X22 --00 0000 --00 0000 --uu uuuu
SPBRG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
RCREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TXREG2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TXSTA2 6X27 6X22 8X27 8X22 0000 0010 0000 0010 uuuu uuuu
RCSTA2 6X27 6X22 8X27 8X22 0000 000x 0000 000x uuuu uuuu
ECCP3AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP3DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP2AS 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
ECCP2DEL 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2BUF 6X27 6X22 8X27 8X22 xxxx xxxx uuuu uuuu uuuu uuuu
SSP2ADD 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2STAT 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2CON1 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
SSP2CON2 6X27 6X22 8X27 8X22 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector
(0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with
the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled
as PORTA pins, they are disabled and read ‘0’.