Information

PIC18F8722 FAMILY
DS39646C-page 438 © 2008 Microchip Technology Inc.
Bus Collision During Start
Condition (SDAx Only) .....................................241
Bus Collision for Transmit and Acknowledge ...........240
Capture/Compare/PWM (All ECCP/CCP
Modules) .......................................................... 405
CLKO and I/O ..........................................................400
Clock Synchronization .............................................226
Clock/Instruction Cycle ..............................................69
EUSART Synchronous Receive
(Master/Slave) ..................................................415
EUSART Synchronous Transmission
(Master/Slave) ..................................................415
Example SPI Master Mode (CKE = 0) .....................407
Example SPI Master Mode (CKE = 1) .....................408
Example SPI Slave Mode (CKE = 0) .......................409
Example SPI Slave Mode (CKE = 1) .......................410
External Clock (All Modes Except PLL) ................... 398
External Memory Bus for Sleep
(Microprocessor Mode) ............................105, 108
External Memory Bus for TBLRD (Extended
Microcontroller Mode) ..............................104, 107
External Memory Bus for TBLRD
(Microprocessor Mode) ....................................107
External Memory Bus for TBLRD with 1 T
CY
Wait State (Microprocessor Mode) .................. 104
Fail-Safe Clock Monitor (FSCM) ..............................316
First Start Bit Timing ................................................234
Full-Bridge PWM Output .......................................... 197
Half-Bridge PWM Output .........................................196
High/Low-Voltage Detect Characteristics ................ 395
High-Voltage Detect Operation
(VDIRMAG = 1) ................................................294
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C Acknowledge Sequence ....................................239
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2
C Bus Data ............................................................411
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2
C Bus Start/Stop Bits .............................................411
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C Master Mode (7 or 10-Bit Transmission) ........... 237
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C Master Mode (7-Bit Reception) ..........................238
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C Slave Mode (10-Bit Reception, SEN = 0) ..........223
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C Slave Mode (10-Bit Reception, SEN = 1) ..........228
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C Slave Mode (10-Bit Transmission) .....................224
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C Slave Mode (7-bit Reception, SEN = 0) .............221
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C Slave Mode (7-Bit Reception, SEN = 1) ............227
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C Slave Mode (7-Bit Transmission) .......................222
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C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) .............229
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C Stop Condition Receive or Transmit Mode ........ 239
Low-Voltage Detect Operation (VDIRMAG = 0) .......293
Master SSP I
2
C Bus Data ........................................413
Master SSP I
2
C Bus Start/Stop Bits ........................ 413
Parallel Slave Port
(PIC18F8527/8622/8627/8722) .......................406
Parallel Slave Port (PSP) Read ............................... 160
Parallel Slave Port (PSP) Write ...............................160
Program Memory Read ............................................401
Program Memory Write ............................................402
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled) .....................................202
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) .....................................202
PWM Direction Change ........................................... 199
PWM Direction Change at Near
100% Duty Cycle .............................................199
PWM Output ............................................................184
Repeated Start Condition .........................................235
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 403
Send Break Character Sequence ............................ 263
Slave Synchronization ............................................. 211
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 55
SPI Mode (Master Mode) ......................................... 210
SPI Mode (Slave Mode, CKE = 0) ........................... 212
SPI Mode (Slave Mode, CKE = 1) ........................... 212
Synchronous Reception (Master Mode, SREN) ...... 266
Synchronous Transmission ..................................... 264
Synchronous Transmission (Through TXEN) .......... 265
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) .......................................... 55
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 1) ...................... 54
Time-out Sequence on Power-up
(MCLR
Not Tied to VDD, Case 2) ...................... 54
Time-out Sequence on Power-up
(MCLR
Tied to VDD, VDD Rise < TPWRT) ........... 54
Timer0 and Timer1 External Clock .......................... 404
Transition for Entry to Idle Mode ................................ 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 314
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) .................. 45
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 44
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 43
Transition to RC_RUN Mode ..................................... 44
Typical Opcode Fetch, 8-Bit Mode .......................... 108
Timing Diagrams and Specifications
A/D Conversion Requirements ................................ 417
AC Characteristics
Internal RC Accuracy ....................................... 399
Capture/Compare/PWM Requirements
(All ECCP/CCP Modules) ................................ 405
CLKO and I/O Requirements ........................... 400, 401
EUSART Synchronous Receive
Requirements .................................................. 415
EUSART Synchronous Transmission
Requirements .................................................. 415
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 407
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 408
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 409
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 410
External Clock Requirements .................................. 398
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C Bus Data Requirements (Slave Mode) .............. 412
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C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 411
Master SSP I
2
C Bus Data Requirements ................ 414
Master SSP I
2
C Bus Start/Stop Bits
Requirements .................................................. 413
Parallel Slave Port Requirements
(PIC18F8527/8622/8627/8722) ....................... 406
PLL Clock ................................................................ 399
Program Memory Write Requirements .................... 402