Information

© 2008 Microchip Technology Inc. DS39646C-page 433
PIC18F8722 FAMILY
RCALL ..................................................................... 351
RESET .....................................................................351
RETFIE ....................................................................352
RETLW ....................................................................352
RETURN ..................................................................353
RLCF ........................................................................353
RLNCF ..................................................................... 354
RRCF ....................................................................... 354
RRNCF ....................................................................355
SETF ........................................................................ 355
SETF (Indexed Literal Offset Mode) ........................ 369
SLEEP ..................................................................... 356
Standard Instructions ............................................... 321
SUBFWB ..................................................................356
SUBLW ....................................................................357
SUBWF .................................................................... 357
SUBWFB ..................................................................358
SWAPF ....................................................................358
TBLRD ..................................................................... 359
TBLWT .....................................................................360
TSTFSZ ...................................................................361
XORLW ....................................................................361
XORWF .................................................................... 362
INTCON Register
RBIF Bit .................................................................... 137
INTCON Registers ........................................................... 121
Inter-Integrated Circuit. See I
2
C.
Internal Oscillator Block ..................................................... 34
Adjustment .................................................................34
INTIO Modes .............................................................. 34
INTOSC Frequency Drift ............................................ 35
INTOSC Output Frequency ........................................ 34
OSCTUNE Register ................................................... 34
PLL in INTOSC Modes .............................................. 35
Internal RC Oscillator
Use with WDT .......................................................... 312
Internet Address ...............................................................439
Interrupt Sources ............................................................. 297
A/D Conversion Complete ....................................... 275
Capture Complete (CCP) ......................................... 181
Compare Complete (CCP) ....................................... 182
Interrupt-on-Change (RB7:RB4) .............................. 137
INTx Pin ...................................................................134
PORTB, Interrupt-on-Change ..................................134
TMR0 .......................................................................134
TMR0 Overflow ........................................................ 163
TMR1 Overflow ........................................................ 165
TMR2 to PR2 Match (PWM) ............................184, 192
TMR3 Overflow ................................................ 173, 175
TMR4 to PR4 Match ................................................ 178
TMR4 to PR4 Match (PWM) ....................................177
Interrupts ..........................................................................119
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ........................................................ 137
INTOSC, INTRC. See Internal Oscillator Block.
IORLW .............................................................................344
IORWF .............................................................................344
IPR Registers ................................................................... 130
K
Key Features
Easy Migration .............................................................8
Expanded Memory ....................................................... 7
External Memory Interface ...........................................8
L
LFSR ............................................................................... 345
Low-Voltage ICSP Programming. See Single-Supply
ICSP Programming
M
Master Clear (MCLR) ......................................................... 51
Master Synchronous Serial Port (MSSP). See MSSP.
Memory
Mode Memory Access ............................................... 64
Memory Maps for PIC18F8722 Family
Program Memory Modes ........................................... 65
Memory Organization ........................................................ 63
Data Memory ............................................................. 72
Program Memory ....................................................... 63
Modes ................................................................ 63
Memory Programming Requirements .............................. 393
Microchip Internet Web Site ............................................. 439
Microcontroller Mode ....................................................... 100
Microprocessor Mode ...................................................... 100
Microprocessor with Boot Block Mode ............................. 100
Migration from Baseline to Enhanced Devices ................ 426
Migration from High-End to Enhanced Devices ............... 427
Migration from Mid-Range to Enhanced Devices ............ 427
MOVF .............................................................................. 345
MOVFF ............................................................................ 346
MOVLB ............................................................................ 346
MOVLW ........................................................................... 347
MOVSF ............................................................................ 365
MOVSS ............................................................................ 366
MOVWF ........................................................................... 347
MPLAB ASM30 Assembler, Linker, Librarian .................. 372
MPLAB ICD 2 In-Circuit Debugger .................................. 373
MPLAB ICE 2000 High-Performance
Universal In-Circuit Emulator ................................... 373
MPLAB Integrated Development
Environment Software ............................................. 371
MPLAB PM3 Device Programmer ................................... 373
MPLAB REAL ICE In-Circuit Emulator System ............... 373
MPLINK Object Linker/MPLIB Object Librarian ............... 372
MSSP
ACK
Pulse ....................................................... 219, 220
Control Registers (general) ..................................... 205
I
2
C Mode. See I
2
C Mode.
Module Overview ..................................................... 205
SPI Master/Slave Connection .................................. 209
TMR4 Output for Clock Shift .................................... 178
MULLW ............................................................................ 348
MULWF ............................................................................ 348
N
NEGF ............................................................................... 349
NOP ................................................................................. 349
O
Opcode Field Descriptions ............................................... 322
Oscillator Configuration ..................................................... 31
EC .............................................................................. 31
ECIO .......................................................................... 31
HS .............................................................................. 31
HSPLL ....................................................................... 31
Internal Oscillator Block ............................................. 34
INTIO1 ....................................................................... 31
INTIO2 ....................................................................... 31
LP .............................................................................. 31