Information

© 2008 Microchip Technology Inc. DS39646C-page 431
PIC18F8722 FAMILY
Data Memory .....................................................................72
Access Bank .............................................................. 74
and the Extended Instruction Set ............................... 83
Bank Select Register (BSR) ....................................... 72
General Purpose Registers ........................................ 74
Map for PIC18F8722 Family ......................................73
Special Function Registers ........................................75
DAW ................................................................................. 340
DC Characteristics ........................................................... 391
Power-Down and Supply Current ............................ 379
Supply Voltage ......................................................... 378
DCFSNZ .......................................................................... 341
DECF ...............................................................................340
DECFSZ ...........................................................................341
Development Support ...................................................... 371
Device Differences ...........................................................425
Device Overview ..................................................................7
Details on Individual Family Members ......................... 9
Features (table) ......................................................9, 10
New Core Features ......................................................7
Device Reset Timers .......................................................... 53
Oscillator Start-up Timer (OST) ................................. 53
PLL Lock Time-out ..................................................... 53
Power-up Timer (PWRT) ...........................................53
Time-out Sequence .................................................... 53
Direct Addressing ...............................................................82
E
ECCP
Capture and Compare Modes .................................. 192
Standard PWM Mode ............................................... 192
Effect on Standard PIC MCU Instructions ........................ 368
Effects of Power-Managed Modes on Various
Clock Sources ............................................................ 40
Electrical Characteristics .................................................. 375
Enhanced Capture/Compare/PWM (ECCP) .................... 187
and Program Memory Modes .................................. 188
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 188
Pin Configurations for ECCP1 ................................. 189
Pin Configurations for ECCP2 ................................. 190
Pin Configurations for ECCP3 ................................. 191
PWM Mode. See PWM (ECCP Module).
Timer Resources ...................................................... 192
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................276
A/D Minimum Charging Time ................................... 276
A/D, Calculating the Minimum Required
Acquisition Time .............................................. 276
Errata ................................................................................... 5
EUSART
Asynchronous Mode ................................................ 257
12-Bit Break Transmit and Receive ................. 263
Associated Registers, Receive ........................ 261
Associated Registers, Transmit ....................... 259
Auto-Wake-up on Sync Break .........................262
Receiver ........................................................... 260
Setting up 9-Bit Mode with
Address Detect ........................................ 260
Transmitter .......................................................257
Baud Rate Generator
Operation in Power-Managed Modes .............. 251
Baud Rate Generator (BRG) ................................... 251
Associated Registers ....................................... 252
Auto-Baud Rate Detect .................................... 255
Baud Rate Error, Calculating ........................... 252
Baud Rates, Asynchronous Modes ................. 253
High Baud Rate Select (BRGH Bit) ................. 251
Sampling ......................................................... 251
Synchronous Master Mode ...................................... 264
Associated Registers, Receive ........................ 267
Associated Registers, Transmit ....................... 265
Reception ........................................................ 266
Transmission ................................................... 264
Synchronous Slave Mode ........................................ 268
Associated Registers, Receive ........................ 269
Associated Registers, Transmit ....................... 268
Reception ........................................................ 269
Transmission ................................................... 268
Extended Instruction Set
ADDFSR .................................................................. 364
ADDULNK ............................................................... 364
CALLW .................................................................... 365
MOVSF .................................................................... 365
MOVSS .................................................................... 366
PUSHL ..................................................................... 366
SUBFSR .................................................................. 367
SUBULNK ................................................................ 367
Extended Microcontroller Mode ....................................... 100
External Clock Input ........................................................... 32
External Memory Bus ........................................................ 97
16-Bit Byte Select Mode .......................................... 103
16-Bit Byte Write Mode ............................................ 101
16-Bit Data Width Modes ......................................... 100
16-Bit Mode Timing ................................................. 104
16-Bit Word Write Mode .......................................... 102
8-Bit Data Width Modes ........................................... 106
8-Bit Mode Timing ................................................... 107
I/O Port Functions ...................................................... 97
Operation in Power-Managed Modes ...................... 109
F
Fail-Safe Clock Monitor ........................................... 297, 315
Exiting Operation ..................................................... 315
Interrupts in Power-Managed Modes ...................... 316
POR or Wake from Sleep ........................................ 316
WDT During Oscillator Failure ................................. 315
Fast Register Stack ........................................................... 68
Firmware Instructions ...................................................... 321
Flash Program Memory ..................................................... 87
Associated Registers ................................................. 95
Control Registers ....................................................... 88
EECON1 and EECON2 ..................................... 88
TABLAT (Table Latch) Register ........................ 90
TBLPTR (Table Pointer) Register ...................... 90
Erase Sequence ........................................................ 92
Erasing ...................................................................... 92
Operation During Code-Protect ................................. 95
Reading ..................................................................... 91
Table Pointer
Boundaries Based on Operation ....................... 90
Table Pointer Boundaries .......................................... 90
Table Reads and Table Writes .................................. 87
Write Sequence ......................................................... 93
Writing To .................................................................. 93
Protection Against Spurious Writes ................... 95
Unexpected Termination ................................... 95
Write Verify ........................................................ 95
FSCM. See Fail-Safe Clock Monitor.