Information

PIC18F8722 FAMILY
DS39646C-page 416 © 2008 Microchip Technology Inc.
TABLE 28-26: A/D CONVERTER CHARACTERISTICS: PIC18F6X27/6X22/8X27/8X22 (INDUSTRIAL)
PIC18LF6X27/6X22/8X27/8X22 (INDUSTRIAL)
FIGURE 28-25: A/D CONVERSION TIMING
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
A01 N
R Resolution — — 10 bit ΔVREF ≥ 3.0V
A03 EIL Integral Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A04 E
DL Differential Linearity Error — — <±1 LSb ΔVREF ≥ 3.0V
A06 EOFF Offset Error — — <±2 LSb ΔVREF ≥ 3.0V
A07 EGN Gain Error — — <±1 LSb ΔVREF ≥ 3.0V
A10 — Monotonicity Guaranteed
(1)
—VSS ≤ VAIN ≤ VREF
A20 ΔVREF Reference Voltage Range
(V
REFH – VREFL)
1.8
3
—
—
—
—
V
V
V
DD < 3.0V
V
DD ≥ 3.0V
A21 V
REFH Reference Voltage High VSS —VREFH V
A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V
A25 VAIN Analog Input Voltage VREFL —VREFH V
A30 Z
AIN Recommended Impedance of
Analog Voltage Source
——2.5kΩ
A40 I
AD A/D Current
from V
DD
PIC18FXXXX — 180 — μA Average current during
conversion
PIC18LFXXXX — 90 — μA
A50 I
REF VREF Input Current
(2)
—
—
—
—
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
V
REFL current is from RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 1, 2)
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY