Information

PIC18F8722 FAMILY
DS39646C-page 410 © 2008 Microchip Technology Inc.
FIGURE 28-18: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 28-19: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE =
1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SSx
↓ to SCKx ↓ or SCKx ↑ Input 3 TCY —ns
71 T
SCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TSCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A T
B2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 TSCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 TDOR SDOx Data Output Rise Time PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
76 T
DOF SDOx Data Output Fall Time — 25 ns
77 T
SSH2DOZ SSx ↑ to SDOx Output High-Impedance 10 50 ns
78 TSCR SCKx Output Rise Time
(Master mode)
PIC18FXXXX — 25 ns
PIC18LFXXXX — 45 ns VDD = 2.0V
79 T
SCF SCKx Output Fall Time (Master mode) — 25 ns
80 TSCH2DOV,
T
SCL2DOV
SDOx Data Output Valid after SCKx
Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
82 T
SSL2DOV SDOx Data Output Valid after SSx ↓
Edge
PIC18FXXXX — 50 ns
PIC18LFXXXX — 100 ns V
DD = 2.0V
83 TSCH2SSH,
T
SCL2SSH
SSx
↑ after SCKx Edge 1.5 TCY + 40 — ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SSx
SCKx
(CKP =
0)
SCKx
(CKP =
1)
SDOx
SDI
70
71 72
82
SDIx
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
MSb In bit 6 - - - - 1 LSb In
80
83
Note: Refer to Figure 28-5 for load conditions.