Information

© 2008 Microchip Technology Inc. DS39646C-page 305
PIC18F8722 FAMILY
REGISTER 25-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1 R/C-1
CP7
(1)
CP6
(1)
CP5
(2)
CP5
(2)
CP3
(3)
CP2 CP1 CP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CP7: Code Protection bit
(1)
1 = Block 7 (01C000-01FFFFh) not code-protected
0 = Block 7 (01C000-01FFFFh) code-protected
bit 6 CP6: Code Protection bit
(1)
1 = Block 6 (01BFFF-018000h) not code-protected
0 = Block 6 (01BFFF-018000h) code-protected
bit 5 CP5: Code Protection bit
(2)
1 = Block 5 (014000-017FFFh) not code-protected
0 = Block 5 (014000-017FFFh) code-protected
bit 4 CP4: Code Protection bit
(2)
1 = Block 4 (010000-013FFFh) not code-protected
0 = Block 4 (010000-013FFFh) code-protected
bit 3 CP3: Code Protection bit
(3)
1 = Block 3 (00C000-00FFFFh) not code-protected
0 = Block 3 (00C000-00FFFFh) code-protected
bit 2 CP2: Code Protection bit
1 = Block 2 (008000-00BFFFh) not code-protected
0 = Block 2 (008000-00BFFFh) code-protected
bit 1 CP1: Code Protection bit
1 = Block 1 (004000-007FFFh) not code-protected
0 = Block 1 (004000-007FFFh) code-protected
bit 0 CP0: Code Protection bit
1 = Block 0 (000800, 001000 or 002000
(4)
-003FFFh) not code-protected
0 = Block 0 (000800, 001000 or 002000
(4)
-003FFFh) code-protected
Note 1: Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set.
2: Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set.
3: Unimplemented in PIC18F6527/8527 devices; maintain this bit set.
4: Boot block size is determined by the BBSIZ<1:0> bits in CONFIG4L.