Information

© 2008 Microchip Technology Inc. DS39646C-page 293
PIC18F8722 FAMILY
24.2 HLVD Setup
The following steps are needed to set up the HLVD
module:
1. Write the value to the HLVDL<3:0> bits that
selects the desired HLVD trip point.
2. Set the VDIRMAG bit to detect high voltage
(VDIRMAG = 1) or low voltage (VDIRMAG = 0).
3. Enable the HLVD module by setting the
HLVDEN bit.
4. Clear the HLVD interrupt flag (PIR2<2>), which
may have been set from a previous interrupt.
5. Enable the HLVD interrupt if interrupts are
desired by setting the HLVDIE and GIE bits
(PIE2<2> and INTCON<7>). An interrupt will not
be generated until the IRVST bit is set.
24.3 Current Consumption
When the module is enabled, the HLVD comparator
and voltage divider are enabled and will consume static
current. The total current consumption, when enabled,
is specified in electrical specification parameter D022B
(Section 28.2 “DC Characteristics”).
Depending on the application, the HLVD module does
not need to be operating constantly. To decrease the
current requirements, the HLVD circuitry may only
need to be enabled for short periods where the voltage
is checked. After doing the check, the HLVD module
may be disabled.
24.4 HLVD Start-up Time
The internal reference voltage of the HLVD module,
specified in electrical specification parameter D420
(Section 28.2 “DC Characteristics”), may be used
by other internal circuitry, such as the Programmable
Brown-out Reset. If the HLVD or other circuits using the
voltage reference are disabled to lower the device’s
current consumption, the reference voltage circuit will
require time to become stable before a low or
high-voltage condition can be reliably detected. This
start-up time, T
IRVST, is an interval that is independent
of device clock speed. It is specified in electrical
specification parameter 36 (Table 28-12).
The HLVD interrupt flag is not enabled until T
IRVST has
expired and a stable reference voltage is reached. For
this reason, brief excursions beyond the set point may
not be detected during this interval. Refer to
Figure 24-2 or Figure 24-3.
FIGURE 24-2: LOW-VOLTAGE DETECT OPERATION (VDIRMAG = 0)
VHLVD
VDD
HLVDIF
VHLVD
VDD
Enable HLVD
TIRVST
HLVDIF may not be set
Enable HLVD
HLVDIF
HLVDIF cleared in software
HLVDIF cleared in software
HLVDIF cleared in software,
CASE 1:
CASE 2:
HLVDIF remains set since HLVD condition still exists
T
IRVST
Internal Reference is stable
Internal Reference is stable
IRVST
IRVST