Information

PIC18F8722 FAMILY
DS39646C-page 280 © 2008 Microchip Technology Inc.
21.8 Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed
as ‘1011’ and that the A/D module is enabled (ADON
bit is set). When the trigger occurs, the GO/DONE
bit
will be set, starting the A/D acquisition and conversion
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH:ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition period is either timed by
the user, or an appropriate T
ACQ time selected before
the Special Event Trigger sets the GO/DONE
bit (starts
a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 21-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60
PIE2
OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60
IPR2 OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60
ADRESH A/D Result Register High Byte 59
ADRESL A/D Result Register Low Byte 59
ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 59
ADCON1 — — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 59
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 59
TRISA TRISA7
(1)
TRISA6
(1)
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 60
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 60
TRISH
(2)
TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 60
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on 64-pin devices.