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PIC18F8722 FAMILY
DS39646C-page 268 © 2008 Microchip Technology Inc.
20.4 EUSART Synchronous
Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTAx<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CKx pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any low-power
mode.
20.4.1 EUSART SYNCHRONOUS
SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSRx register and transmit.
b) The second word will remain in the TXREGx
register.
c) Flag bit, TXxIF, will not be set.
d) When the first word has been shifted out of
TSRx, the TXREGx register will transfer the
second word to the TSRx and flag bit, TXxIF, will
now be set.
e) If enable bit, TXxIE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1. Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. Clear bits, CREN and SREN.
3. If interrupts are desired, set enable bit, TXxIE.
4. If 9-bit transmission is desired, set bit, TX9.
5. Enable the transmission by setting enable bit,
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISG
— — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 60
RCSTAx SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 59
TXREGx EUSARTx Transmit Register 59
TXSTAx CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 59
BAUDCONx
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 61
SPBRGHx EUSARTx Baud Rate Generator Register High Byte 61
SPBRGx EUSARTx Baud Rate Generator Register Low Byte 59
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.