Information

© 2008 Microchip Technology Inc. DS39646C-page 245
PIC18F8722 FAMILY
TABLE 19-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 57
PIR1 PSPIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 60
PIE1 PSPIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 60
IPR1
PSPIP ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 60
PIR2 OSCFIF CMIF — EEIF BCL1IF HLVDIF TMR3IF CCP2IF 60
PIE2 OSCFIE CMIE — EEIE BCL1IE HLVDIE TMR3IE CCP2IE 60
IPR2
OSCFIP CMIP — EEIP BCL1IP HLVDIP TMR3IP CCP2IP 60
PIR3 SSP2IF BCL2IF RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF 60
PIE3 SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE 60
IPR3 SSP2IP BCL2IP
RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP 60
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 60
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 60
SSP1BUF MSSP1 Receive Buffer/Transmit Register 58
SSP2BUF MSSP2 Receive Buffer/Transmit Register 61
SSP1ADD MSSP1 Address Register in I
2
C™ Slave mode. MSSP1 Baud Rate Reload Register in I
2
C
Master mode.
58
SSP2ADD MSSP2 Address Register in I
2
C Slave mode. MSSP2 Baud Rate Reload Register in I
2
C
Master mode.
61
TMR2 Timer2 Register 58
PR2 Timer2 Period Register 58
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 58
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 58
SSP1STAT SMP CKE D/A
PSR/WUA BF 58
SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 61
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 61
SSP2STAT SMP CKE D/A
PSR/WUA BF 61
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I
2
C mode.